ICS513 Datasheet: PLL Clock Generator





ICS513 Datasheet PDF

Part Number ICS513
Description PLL Clock Generator
Manufacture Integrated Circuit Systems
Total Page 4 Pages
PDF Download Download ICS513 Datasheet PDF

Features: www.DataSheet4U.com ICS513 LOCO™ PLL Clock Generator Features • Packaged a s 8 pin SOIC • ICS’ lowest cost PLL clock plus reference • Produces comm on computer frequencies • Input cryst al frequency typically 14.3182 MHz • Output clock frequencies up to 100 MHz • Low jitter - 40 ps one sigma • Co mpatible with all popular CPUs • Duty cycle of 45/55 • Custom frequencies available • Operating voltages of 3.0 to 5.5 V • Power down mode turns off chip • 25mA drive capability at TTL levels • Advanced, low power CMOS pro cess Description The ICS513 LOCO™ is the most cost effective way to generat e a high quality, high frequency clock output from a 14.31818 MHz crystal or c lock input. The name LOCO stands for LO w Cost Oscillator, as it is designed to replace crystal oscillators in many el ectronic systems. Using Phase-Locked-Lo op (PLL) techniques, the device uses a standard, inexpensive crystal to produc e output clocks up to 100 MHz. Stored in the chip’s ROM is the ability to generate 5 different .

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www.DataSheet4U.com
ICS513
LOCO™ PLL Clock Generator
Description
The ICS513 LOCO™ is the most cost effective
way to generate a high quality, high frequency
clock output from a 14.31818 MHz crystal or
clock input. The name LOCO stands for LOw
Cost Oscillator, as it is designed to replace crystal
oscillators in many electronic systems. Using
Phase-Locked-Loop (PLL) techniques, the device
uses a standard, inexpensive crystal to produce
output clocks up to 100 MHz.
Stored in the chip’s ROM is the ability to generate
5 different output frequencies, allowing one chip
to work in different speed processor systems.
The device also has a power down mode that turns
off the clock outputs when both select pins are low.
In this mode, the internal PLL is not running.
Block Diagram
VDD GND
Features
• Packaged as 8 pin SOIC
• ICS’ lowest cost PLL clock plus reference
• Produces common computer frequencies
• Input crystal frequency typically 14.3182 MHz
• Output clock frequencies up to 100 MHz
• Low jitter - 40 ps one sigma
• Compatible with all popular CPUs
• Duty cycle of 45/55
• Custom frequencies available
• Operating voltages of 3.0 to 5.5 V
• Power down mode turns off chip
• 25mA drive capability at TTL levels
• Advanced, low power CMOS process
S1, S0
14.31818 MHz
crystal
or clock X1/ICLK
X2
2
Crystal
Oscillator
PLL
Clock
Synthesis
and Control
Circuitry
Optional crystal capacitors
Output
Buffer
CLK
Output
Buffer
REF
MDS 513 B
1
Revision 080699
Printed 12/4/00
Integrated Circuit Systems • 525 Race Street • San Jose • CA• 95126 • (408)295-9800tel• (408)295-9818fax

           






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