Clock Generator. ICS514 Datasheet

ICS514 Generator. Datasheet pdf. Equivalent

Part ICS514
Description PLL Clock Generator
Feature www.DataSheet4U.com ICS514 LOCO™ PLL Clock Generator Features • Packaged as 8 pin SOIC • ICS’ lowes.
Manufacture Integrated Circuit Systems
Datasheet
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LOCO™ PLL CLOCK GENERATOR DATASHEET ICS514 Description The ICS514 Datasheet
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ICS514
www.DataSheet4U.com
ICS514
LOCO™ PLL Clock Generator
Description
The ICS514 LOCO™ is the most cost effective
way to generate a high quality, high frequency
clock output from a 14.31818 MHz crystal or
clock input. The name LOCO stands for LOw
Cost Oscillator, as it is designed to replace crystal
oscillators in many electronic systems. Using
Phase-Locked-Loop (PLL) techniques, the device
uses a standard, inexpensive crystal to produce
output clocks up to 66.66 MHz.
Stored in the chip’s ROM is the ability to generate
5 different output frequencies, allowing one chip
to work in different speed processor systems.
The device also has a power down mode that turns
off the clock outputs when both select pins are low.
In this mode, the internal PLL is not running.
Block Diagram
VDD GND
Features
• Packaged as 8 pin SOIC
• ICS’ lowest cost PLL clock plus reference
• Produces common computer frequencies
• Input crystal frequency typically 14.3182 MHz
• Output clock frequencies up to 66.66 MHz
• Low jitter - 40 ps one sigma
• Compatible with all popular CPUs
• Duty cycle of 45/55
• Custom frequencies available
• Operating voltages of 3.0 to 5.5 V
• Power down mode turns off chip
• 25mA drive capability at TTL levels
• Advanced, low power CMOS process
S1, S0
14.31818 MHz
crystal or clock
X1/ICLK
X2
2
Crystal
Oscillator
PLL
Clock
Synthesis
and Control
Circuitry
Optional crystal capacitors
Output
Buffer
CLK
Output
Buffer
REF
MDS 514 B
1
Revision 080699
Printed 11/13/00
Integrated Circuit Systems • 525 Race Street • San Jose•CA • 95126 • (408)295-9800tel• (408)295-9818fax



ICS514
www.DataSheet4U.com
ICS514
LOCO™ PLL Clock Generator
Pin Assignment
X1/ICLK
VDD
GND
REF
1
2
3
4
8 X2
7 S1
6 S0
5 CLK
Clock Decoding Table (MHz) with
14.31818MHz Crystal or Clock Input
S1 S0
CLK Multiplier Accuracy
0 0 Power Down CLK -
-
01
25
1.746
1 ppm
M0
33.33
2.328 0.008%
M1
40
2.794
1 ppm
10
50
3.492
1 ppm
11
66.66
4.656 0.008%
0 = connect directly to ground.
1 = connect directly to VDD.
M = leave unconnected (floating).
CLK and REF stop low in power down state.
Pin Descriptions
Number
1
2
3
4
5
6
7
8
Name
X1/ICLK
VDD
GND
REF
CLK
S0
S1
X2
Type
I
P
P
O
O
TI
TI
O
Description
Crystal connection to 14.31818 MHz crystal or clock input.
Connect to +3.3V or +5V.
Connect to ground.
Reference 14.31818 MHz crystal oscillator buffered clock output.
Clock output per table above.
Select 0 for output clock. Connect to GND or VDD or float. See table above.
Select 1 for output clock. Connect to GND or VDD or float. See table above.
Crystal connection to 14.31818 MHz crystal. Leave unconnected for clock input.
Key: I = Input, TI = Tri-Level Input, O = output, P = power supply connection
Notes: 1. With S1 = S0 = 0, the internal PLL is turned off and the CLK output stops low.
The crystal oscillator and REF output are still active.
2. With a clock input, the phase relationship between the input and output clocks can
change each time the device is powered on. If a fixed phase relationship is required,
please use our ICS571 or other zero delay multipliers.
MDS 514 B
2
Revision 080699
Printed 11/13/00
Integrated Circuit Systems • 525 Race Street • San Jose•CA • 95126 • (408)295-9800tel• (408)295-9818fax





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