FANOUT BUFFER. ICS5310I-01 Datasheet

ICS5310I-01 BUFFER. Datasheet pdf. Equivalent

Part ICS5310I-01
Description ECL/LVPECL FANOUT BUFFER
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ICS5310I-01
www.DataSheet4U.com Integrated
Circuit
Systems, Inc.
ICS85310I-01
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS85310I-01 is a low skew, high perfor-
ICS mance 1-to-10 Differential-to-2.5V/3.3V ECL/
HiPerClockS™ LVPECL Fanout Buffer and a member of the
HiPerClockS™ family of High Perfor mance
Clock Solutions from ICS. The CLKx, nCLKx
pairs can accept most standard differential input levels. The
ICS85310I-01 is characterized to operate from either a
2.5V or a 3.3V power supply. Guaranteed output and part-
to-part skew characteristics make the ICS85310I-01 ideal
for those clock distribution applications demanding well
defined performance and repeatability.
FEATURES
Ten differential 2.5V/3.3V LVPECL / ECL outputs
Two selectable differential input pairs
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum output frequency: 700MHz
Translates any single ended input signal to
3.3V LVPECL levels with resistor bias on nCLK input
Output skew: 30ps (typical)
Part-to-part skew: 140ps (typical)
Propagation delay: 2ns (typical)
Additive phase jitter, RMS: <0.13ps (typical)
LVPECL mode operating voltage supply range:
V = 2.375V to 3.8V, V = 0V
CC EE
ECL mode operating voltage supply range:
VCC = 0V, VEE = -2.375V to -3.8V
-40°C to 85°C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
CLK0
nCLK0
CLK1
nCLK1
0
1
CLK_SEL
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
32 31 30 29 28 27 26 25
VCC 1
24 Q3
Q3
nQ3
CLK_SEL
CLK0
2
3
23 nQ3
22 Q4
Q4
nQ4
nCLK0 4 ICS85310I-01 21 nQ4
nc 5
20 Q5
Q5
nQ5
CLK1
nCLK1
6
7
19 nQ5
18 Q6
Q6
nQ6
VEE 8
17 nQ6
9 10 11 12 13 14 15 16
Q7
nQ7
Q8 32-Lead LQFP
nQ8 7mm x 7mm x 1.4mm package body
Q9
nQ9
Y Package
Top View
85310AYI-01
www.icst.com/products/hiperclocks.html
1
REV. F JANUARY16, 2006



ICS5310I-01
www.DataSheet4U.com Integrated
Circuit
Systems, Inc.
ICS85310I-01
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1 VCC Power
Positive supply pin.
2
CLK_SEL
Input
Pulldown
Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW,
selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels.
3
CLK0
Input Pulldown Non-inverting differential clock input.
4 nCLK0 Input Pullup Inverting differential clock input.
5 nc Unused
No connect.
6 CLK1 Input Pulldown Non-inverting differential clock input.
7 nCLK1 Input Pullup Inverting differential clock input.
8
9, 16, 25, 32
10, 11
VEE
V
CCO
nQ9, Q9
Power
Power
Output
Negative supply pin.
Output supply pins.
Differential output pair. LVPECL interface levels.
12, 13
nQ8, Q8 Output
Differential output pair. LVPECL interface levels.
14, 15
nQ7, Q7 Output
Differential output pair. LVPECL interface levels.
17, 18
nQ6, Q6 Output
Differential output pair. LVPECL interface levels.
19, 20
nQ5, Q5 Output
Differential output pair. LVPECL interface levels.
21, 22
nQ4, Q4 Output
Differential output pair. LVPECL interface levels.
23, 24
nQ3, Q3 Output
Differential output pair. LVPECL interface levels.
26, 27
nQ2, Q2 Output
Differential output pair. LVPECL interface levels.
28, 29
nQ1, Q1 Output
Differential output pair. LVPECL interface levels.
30, 31
nQ0, Q0 Output
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
RPULLUP
RPULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
85310AYI-01
www.icst.com/products/hiperclocks.html
2
REV. F JANUARY16, 2006





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