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BUK95/96/9E4R4-40B
TrenchMOS™ logic level FET
Rev. 02 — 13 October 2003 Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect power transistor in a plastic package using Philips High-Performance Automotive (HPA) TrenchMOS™ technology.
1.2 Features
s Very low on-state resistance s 175 °C rated s Q101 compliant s Logic level compatible.
1.3 Applications
s Automotive systems s Motors, lamps and solenoids s 12 V loads s General purpose power switching.
1.4 Quick reference data
s EDS(AL)S ≤ 961 mJ s ID ≤ 75 A s RDSon = 3.9 mΩ (typ) s Ptot ≤ 254 W.
2. Pinning information
Table 1: Pin 1 2 3 mb Pinning - SOT78, SOT404, and SOT226 simplified outlines and symbol Description gate (g) drain (d) source (s) mounting base, connected to drain (d)
2 1
MBK106
Simplified outline
[1]
Symbol
mb mb d
mb
g s
MBB076
3
MBK116
1 2 3
MBK112
1 2 3
SOT78 (TO-220AB)
[1]
SOT404 (D2-PAK)
SOT226 (I2-PAK)
It is not possible to make connection to pin 2 of the SOT404 package.
Philips Semiconductors
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BUK95/96/9E4R4-40B
TrenchMOS™ logic level FET
3. Ordering information
Table 2: Ordering information Package Name BUK954R4-40B BUK964R4-40B BUK9E4R4-40B TO-220AB D2-PAK I2-PAK Description Plastic single-ended heat-sink mounted package Plastic single-ended surface mounted package Plastic single-ended low-profile package Version SOT78 SOT404 SOT226 Type number
4. Limiting values
Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage (DC) drain current (DC) Tmb = 25 °C; VGS = 5 V; Figure 2 and 3 Tmb = 100 °C; VGS = 5 V; Figure 2 IDM Ptot Tstg Tj IDR IDRM peak drain current total power dissipation storage temperature junction temperature reverse drain current (DC) peak reverse drain current Tmb = 25 °C Tmb = 25 °C; pulsed; tp ≤ 10 µs unclamped inductive load; ID = 75 A; VDS ≤ 40 V; VGS = 5 V; RGS = 50 Ω; starting Tmb = 25 °C
[1] [2] [1] [2] [2]
Conditions RGS = 20 kΩ
Min −55 −55 -
Max 40 40 ±15 174 75 75 697 254 +175 +175 174 75 697 961
Unit V V V A A A A W °C °C A A A mJ
Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 Tmb = 25 °C; Figure 1
Source-drain diode
Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy
[1] [2]
Current is limited by power dissipation chip rating Continuous current is limited by package.
9397 750 12051
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 13 October 2003
2 of 16
Philips Semiconductors
www.DataSheet4U.com
BUK95/96/9E4R4-40B
TrenchMOS™ logic level FET
120 Pder (%)
03na19
200 ID (A) 150
03nl57
80
100
40 Capped at 75 A due to package 50
0 0 50 100 150 200 Tmb (° C)
0 0 50 100 150 200 Tmb (°C)
P tot P der = ---------------------- × 100 % P °
tot ( 25 C )
VGS ≥ 5 V
Fig 1. Normalized total power dissipation as a function of mounting base temperature.
Fig 2. Continuous drain current as a function of mounting base temperature.
103 Limit RDSon = VDS/ID
03nl58
ID (A)
tp = 10 µ s
102
100 µ s
Capped at 75 A due to package
1 ms
10 ms 10 DC 100 ms
1 10-1
1
10
VDS (V)
102
Tmb = 25 °C; IDM single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 12051
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 13 October 2003
3 of 16
Philips Semiconductors
www.DataSheet4U.com
BUK95/96/9E4R4-40B
TrenchMOS™ logic level FET
5. Thermal characteristics
Table 4: Rth(j-mb) Rth(j-a) Thermal characteristics Conditions Min Typ Max Unit 0.59 K/W thermal resistance from junction to mounting Figure 4 base thermal resistance from junction to ambient SOT78 (TO-220AB) SOT226 (I2-PAK) SOT404 (D2-PAK) vertical in still air vertical in still air minimum footprint; mounted on a PCB 60 60 50 K/W K/W K/W Symbol Parameter
5.1 Transient thermal impedance
1 Zth(j-mb) (K/W) δ = 0.5 0.2 10-1 0.1 0.05 0.02 10-2 P
03nl59
δ=
tp T
single shot tp T 10-3 10-6 10-5 10-4 10-3 10-2 10-1 tp (s) 1 t
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 12051
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 13 October 2003
4 of 16
Philips Semiconductors
www.DataSheet4U.com
BUK95/96/9E4R4-40B
TrenchMOS™ logic level FET
6. Characteristics
Table 5: Characteristics Tj = 25 °C unless otherwise specified Symbol V(BR)DSS Parameter drain-source breakdown voltage Conditions ID = 0.25 mA; VGS = 0 V Tj = 25 °C Tj = −55 °C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 9 Tj = 25 °C Tj = 175 °C Tj = −55 °C IDSS drain-source leakage current VDS = 40 V; VGS = 0 V Tj = 25 °C Tj = 175 °C IGSS RDSon gate-source leakage current drain-source on-state resistance VGS = ±15 V; VDS = 0 V VGS = 5 V; ID = 25 A; Figure 7 and 8 Tj = 25 °C Tj = .