AD9251 Datasheet: 1.8 V Dual Analog-to-Digital Converter





AD9251 1.8 V Dual Analog-to-Digital Converter Datasheet

Part Number AD9251
Description 1.8 V Dual Analog-to-Digital Converter
Manufacture Analog Devices
Total Page 30 Pages
PDF Download Download AD9251 Datasheet PDF

Features: Data Sheet 14-Bit, 20 MSPS/40 MSPS/65 M SPS/80 MSPS, 1.8 V Dual Analog-to-Digit al Converter AD9251 07938-001 FEATURE S 1.8 V analog supply operation 1.8 V t o 3.3 V output supply SNR 74.3 dBFS at 9.7 MHz input 71.5 dBFS at 200 MHz inpu t SFDR 93 dBc at 9.7 MHz input 80 dBc a t 200 MHz input Low power 33 mW per cha nnel at 20 MSPS 73 mW per channel at 80 MSPS Differential input with 700 MHz b andwidth On-chip voltage reference and sample-and-hold circuit 2 V p-p differe ntial analog input DNL = ±0.45 LSB Ser ial port control options Offset binary, gray code, or twos complement data for mat Optional clock duty cycle stabilize r Integer 1-to-8 input clock divider Da ta output multiplex option Built-in sel ectable digital test pattern generation Energy-saving power-down modes Data cl ock out with programmable clock and dat a alignment APPLICATIONS Communications Diversity radio systems Multimode digi tal receivers GSM, EDGE, W-CDMA, LTE, C DMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna .

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Data Sheet
14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
1.8 V Dual Analog-to-Digital Converter
AD9251
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR
74.3 dBFS at 9.7 MHz input
71.5 dBFS at 200 MHz input
SFDR
93 dBc at 9.7 MHz input
80 dBc at 200 MHz input
Low power
33 mW per channel at 20 MSPS
73 mW per channel at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.45 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data
alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Battery-powered instruments
Hand held scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
FUNCTIONAL BLOCK DIAGRAM
AVDD
GND
SDIO SCLK CSB
VIN+A
VIN–A
VREF
SENSE
VCM
RBIAS
VIN–B
VIN+B
REF
SELECT
SPI
ADC
PROGRAMMING DATA
AD9251
ADC
DIVIDE DUTY CYCLE
1 TO 8 STABILIZER
MODE
CONTROLS
ORA
D13A
D0A
DCOA
DRVDD
ORB
D13B
D0B
DCOB
CLK+ CLK–
SYNC
DCS
Figure 1.
PDWN DFS OEB
PRODUCT HIGHLIGHTS
1. The AD9251 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
2. The patented sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
3. A standard serial port interface supports various product
features and functions, such as data output formatting,
internal clock divider, power-down, DCO/DATA timing
and offset adjustments, and voltage reference modes.
4. The AD9251 is packaged in a 64-lead RoHS compliant
LFCSP that is pin compatible with the AD9268 16-bit
ADC, the AD9258 14-bit ADC, the AD9231 12-bit ADC,
and the AD9204 10-bit ADC, enabling a simple migration
path between 10-bit and 16-bit converters sampling from
20 MSPS to 125 MSPS.
Rev. B
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Tel: 781.329.4700 ©2009–2016 Analog Devices, Inc. All rights reserved.
Technical Support
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