FPD-Link Serializer/Deserializer. DS90UR241Q Datasheet

DS90UR241Q Serializer/Deserializer. Datasheet pdf. Equivalent

Part DS90UR241Q
Description 5-43 MHz DC-Balanced 24-Bit FPD-Link Serializer/Deserializer
Feature DS90UR241Q/DS90UR124Q 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset w.
Manufacture National Semiconductor
Datasheet
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DS90UR241Q/DS90UR124Q 5-43 MHz DC-Balanced 24-Bit FPD-Link I DS90UR241Q Datasheet
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DS90UR241Q
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DS90UR241Q
DS90UR124Q
September 4, 2009
5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and
Deserializer Chipset
General Description
The DS90UR241/124 Chipset translates a 24-bit parallel bus
into a fully transparent data/control FPD-Link II LVDS serial
stream with embedded clock information. This chipset is ide-
ally suited for driving graphical data to displays requiring 18-
bit color depth - RGB666 + HS, VS, DE + 3 additional general
purpose data channels. This single serial stream simplifies
transferring a 24-bit bus over PCB traces and cable by elim-
inating the skew problems between parallel data and clock
paths. It saves system cost by narrowing data paths that in
turn reduce PCB layers, cable width, and connector size and
pins.
The DS90UR241/124 incorporates FPD-Link II LVDS signal-
ing on the high-speed I/O. FPD-Link II LVDS provides a low
power and low noise environment for reliably transferring data
over a serial transmission path. By optimizing the Serializer
output edge rate for the operating frequency range EMI is fur-
ther reduced.
In addition, the device features pre-emphasis to boost signals
over longer distances using lossy cables. Internal DC bal-
anced encoding/decoding is used to support AC-Coupled
interconnects. Using National Semiconductor’s proprietary
random lock, the Serializer’s parallel data are randomized to
the Deserializer without the need of REFCLK.
Features
Supports displays with 18-bit color depth
5MHz to 43MHz pixel clock
Automotive grade product AEC-Q100 grade 2 qualified
24:1 interface compression
Embedded clock with DC Balancing supports AC-coupled
data transmission
Capable to drive up to 10 meters shielded twisted-pair
cable
No reference clock required (deserializer)
Meets ISO 10605 ESD - Greater than 8 kV HBM ESD
structure
Hot plug support
EMI Reduction - Serializer accepts spread spectrum input;
data randomization and shuffling on serial link;
Deserializer provides Adjustable PTO (progressive turn-
on) LVCMOS outputs
@Speed BIST (built-in self test) to validate LVDS
transmission path
Individual power-down controls for both Transmitter and
Receiver
Power supply range 3.3V ± 10%
48-pin TQFP package for Transmitter and 64-pin TQFP
package for Receiver
Temperature range -40°C to +105°C
Backward compatible mode with DS90C241/DS90C124
Applications
Automotive Central Information Display
Automotive Instrument Cluster Display
Automotive Heads-Up Display
Remote Camera-based Driver Assistance Systems
Applications Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2009 National Semiconductor Corporation 201945
20194527
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DS90UR241Q
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Ordering Information
NSID
DS90UR241QVS
DS90UR241QVSX
DS90UR241IVS
DS90UR241IVSX
DS90UR124QVS
DS90UR124QVSX
DS90UR124IVS
DS90UR124IVSX
Package Type
48-Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch
48-Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch
48-Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch
48-Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch
64-Lead TQFP style, 10.0 X 10.0 X 1.0 mm, 0.5 mm pitch
64-Lead TQFP style, 10.0 X 10.0 X 1.0 mm, 0.5 mm pitch
64-Lead TQFP style, 10.0 X 10.0 X 1.0 mm, 0.5 mm pitch
64-Lead TQFP style, 10.0 X 10.0 X 1.0 mm, 0.5 mm pitch
20194501
Package ID
VBC48A
VBC48A
VBC48A
VBC48A
VEC64A
VEC64A
VEC64A
VEC64A
Quantity
1000
1000
1000
1000
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