M13S2561616A

www.DataSheet4U.com ESMT Revision History Revision 0.1 (28 Apr. 2006) - Original M13S2561616A Revision 1.0 (07 Jun. 2006) - Delete Preliminary at ever page - Revise typing error of page1 Revision 1.1 (09 May. 2007) - Modify PD, DC specifications and MRS Revision 1.2 (12 Jun. 2007) - Modify tDQSS Revision 1.3 (13 Jul. 2007) - Add -4 speed grade Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.3 1/48 www.DataSheet4U.com ESMT DDR SDRAM Features z z z z z z z z z z z z z z z z z z z z M13S2561616A 4M x 16 Bit x 4 Banks Double Data Rate SDRAM JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 2; 2.5; 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8 All inputs except data & DM are sampled at the rising edge of the system clock(CLK) Data I/O transitions on both edges of data strobe (DQS) DQS is edge-aligned with data for reads; center-aligned with data for WRITE Data mask (DM) for write masking only VDD = 2.3V ~ 2.7V, VDDQ = 2.3V ~ 2.7V VDD = 2.6V ~ 2.8V, VDDQ = 2.6V ~ 2.8V (only for speed -4) Auto & Self refresh 7.8us refresh interval SSTL-2 I/O interface 66pin TSOPII package Ordering information : PRODUCT NO. M13S2561616A -4TG M13S2561616A -5TG M13S2561616A -6TG MAX FREQ 250MHz 200MHz 166MHz VDD 2.7V 2....