AS4DDR264M72PBG1

i PEM 4.8 G b SDRAM-DDR2 Gb Austin Semiconductor, Inc. AS4DDR264M72PBG1 64Mx72 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit FEATURES „ „ „ DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Military Temp Package: Proprietary Enchanced Die Stacked iPEM 208 Plastic Ball Grid Array (PBGA), 16 x 23mm 1.00mm ball pitch Differential data strobe (DQS, DQS#) per byte Internal, pipelined, double data rate architecture 4n-bit prefetch architecture DLL for alignment of DQ and DQS transitions with clock signal Eight internal banks for concurrent operation (Per DDR2 SDRAM Die) Programmable Burst lengths: 4 or 8 Auto Refresh and Self Refresh Modes (I/T Version) On Die Termination (ODT) Adjustable data – output drive strength 1.8V ±0.1V common core power and I/O supply Programmable CAS latency: 3, 4, 5, 6 or 7 Posted CAS additive latency: 0, 1, 2, 3, 4 or 5 Write latency = Read latency - 1* tCK Organized as 64M x 72 Weight: AS4DDR264M72PBG1 ~ 2.0 grams typical BENEFITS „ „ „ „ „ „ „ 61% Space Savings 55% I/O reduction vs Individual package approach Reduced part count Reduced trace lengths for lower parasitic capacitance Suitable for hi-reliability applications Upgradable to 128M x 72 density in future Pin/Function equivalent to White W3H64M72E-xBSx „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ ConfigurationAddressing Parameter Configuration RefreshCount RowAddress BankAddress ColumnAddress 64Megx72 8Megx16x8Banks 8K A0ͲA12(8k) BA0ͲB...