Document
COTS PEM
Austin Semiconductor, Inc. AS5SP512K18DQ SSRAM
9Mb, 512K x 18, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
NC
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A A CE1\ CE2 NC NC BWb\ BWa\ CE3\ VDD VSS CLK GW\ BWE\ OE\ ADSC\ ADSP\ ADV\ A A
Plastic Encapsulated Microcircuit
80 79 78 77 76 75 74 73 72 71 70 69 68 67
Features
• • • • • • • • • • • • • • • • • Synchronous Operation in relation to the input Clock 2 Stage Registers resulting in Pipeline operation On chip address counter (base +3) for Burst operations Self-Timed Write Cycles On-Chip Address and Control Registers Byte Write support Global Write support On-Chip low power mode [powerdown] via ZZ pin Interleaved or Linear Burst support via Mode pin Three Chip Enables for ease of depth expansion without Data Contention. Two Cycle load, Single Cycle Deselect Asynchronous Output Enable (OE\) Three Pin Burst Control (ADSP\, ADSC\, ADV\) 3.3V Core Power Supply 3.3V/2.5V IO Power Supply JEDEC Standard 100 pin TQFP Package, MS026-D/BHA Available in Industrial, Enhanced, and Mil-Temperature Operating Ranges
NC NC VDDQ VSSQ NC NC DQb DQb VSSQ VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSSQ DQb DQb DQPb NC VSSQ VDDQ NC NC NC
A NC NC VDDQ VSSQ NC DQPa DQa DQa VSSQ VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa NC NC VSSQ VDDQ NC NC NC
SSRAM [SPB]
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MODE A A A A A1 A0
Fast Access Times
Parameter Cycle Time Clock Access Time Output Enable Access Time Symbol tCYC tCD tOE 200Mhz 5.0 3.0 3.0 166Mhz 6.0 3.5 3.5 133Mhz 7.5 4.0 4.0 Units ns ns ns
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Block Diagram
OE\ ZZ CLK CE1\ CE2 CE3\ BWE\ BWx\ GW\ ADV ADSC\ ADSP\ MODE A0-Ax
BURST CNTL. Address Registers Row Decode Column Decode CONTROL BLOCK
General Description
ASI’s AS5SP512K18DQ is a 9.0Mb High Performance Synchronous Pipeline Burst SRAM, available in multiple temperature screening levels, fabricated using High Performance CMOS technology and is organized as a 512K x 18. It integrates address and control registers, a two (2) bit burst address counter supporting four (4) double-word transfers. Writes are internally self-timed and synchronous to the rising edge of clock. ASI’s AS5SP512K18DQ includes advanced control options including Global Write, Byte Write as well as an Asynchronous Output enable. Burst Cycle controls are handled by three (3) input pins, ADV, ADSP\ and ADSC\. Burst operation can be initiated with either the Address Status Processor (ADSP\) or Address Status Cache controller (ADSC\) inputs. Subsequent burst addresses are generated internally in the system’s burst sequence control block and are controlled by Address Advance (ADV) control input.
I/O Gating and Control
Memory Array x18 SBP
❑ Synchronous Pipeline Burst ❋ Two (2) cycle load ❋ One (1) cycle de-select ❋ One (1) cycle latency on Mode change
Output Register
Output Driver
DQx, DQPx
Input Register
AS5SP512K18DQ Revision 1.0 04/04/04
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com
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VDD NC* A A A A A A A A
NC* NC* VSS
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COTS PEM
Austin Semiconductor, Inc.
Pin Description/Assignment Table
Signal Name Clock Address Address Symbol CLK A0, A1 A Type Input Input Input(s) Pin Description This input registers the address, data, enables, Global and Byte writes as well as the burst control functions 37, 36 Low order, Synchronous Address Inputs and Burst counter address inputs 35, 34, 33, 32, 31, 100, Synchronous Address Inputs 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 43,83 98, 92 Active Low True Chip Enables 97 Active High True Chip Enable 88 Active Low True Global Write enable. Write to all bits 93, 94 Active Low True Byte Write enables. Write to byte segments 89 87 86 85
AS5SP512K18DQ SSRAM
Chip Enable Chip Enable Global Write Enable Byte Enables Byte Write Enable Output Enable Address Strobe Controller
CE1\, CE3\ CE2 GW\ BWa\, BWb\ BWE\ OE\ ADSC\
Input Input Input Input Input Input Input
Address Strobe from Processor
ADSP\
Input
Address Advance Power-Down Data Parity Input/Outputs
ADV ZZ DQPa, DQPb
Input Input Input/ Output
Data Input/Outputs
DQa, DQb, DQc Input/ DQd Output
Burst Mode Power Supply [Core] Ground [Core] Power Supply I/O I/O Ground No Connection(s)
MODE VDD VSS VDDQ VSSQ NC
Input Supply Supply Supply Supply NA
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Active Low True Byte Write Function enable Active Low True Asynchronous Output enable Address Strobe from Controller. When asserted LOW, Address is captured in the address registers and A0-A1 are loaded into the Burst When ADSP\ and ADSC are both asserted, only ADSP is recognized 84 Synchronous Address Strobe from Processor. When as.