ADC. AD7193 Datasheet

AD7193 Datasheet PDF


Part

AD7193

Description

24-Bit Sigma-Delta ADC

Manufacture

Analog Devices

Page 30 Pages
Datasheet
Download AD7193 Datasheet


AD7193 Datasheet
Data Sheet
4-Channel, 4.8 kHz, Ultralow Noise,
24-Bit Sigma-Delta ADC with PGA
AD7193
FEATURES
Pressure measurement
Fast settling filter option
4 differential/8 pseudo differential input channels
RMS noise: 11 nV @ 4.7 Hz (gain = 128)
15.5 noise-free bits @ 2.4 kHz (gain = 128)
Up to 22 noise-free bits (gain = 1)
Temperature measurement
Flow measurement
Weigh scales
Chromatography
Medical and scientific instrumentation
Offset drift: ±5 nV/°C
Gain drift: ±1 ppm/°C
Specified drift over time
Automatic channel sequencer
Programmable gain (1 to 128)
Output data rate: 4.7 Hz to 4.8 kHz
Internal or external clock
GENERAL DESCRIPTION
The AD7193 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise,
24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC).
The on-chip low noise gain stage means that signals of small
amplitude can interface directly to the ADC.
Simultaneous 50 Hz/60 Hz rejection
The device can be configured to have four differential inputs or
4 general-purpose digital outputs
eight pseudo differential inputs. The on-chip channel sequencer
Power supply
allows several channels to be enabled simultaneously, and the
AVDD: 3 V to 5.25 V
DVDD: 2.7 V to 5.25 V
Current: 4.65 mA
AD7193 sequentially converts on each enabled channel, simplifying
communication with the part. The on-chip 4.92 MHz clock can
be used as the clock source to the ADC or, alternatively, an external
Temperature range: −40°C to +105°C
clock or crystal can be used. The output data rate from the part
28-lead TSSOP and 32-lead LFCSP packages
can be varied from 4.7 Hz to 4.8 kHz.
Interface
3-wire serial
SPI, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
The device has a very flexible digital filter, including a fast
settling option. Variables such as output data rate and settling
time are dependent on the option selected. The AD7193 also
includes a zero latency option.
APPLICATIONS
The part operates with a power supply from 3 V to 5.25 V. It
PLC/DCS analog input modules
consumes a current of 4.65 mA, and it is available in a 28-lead
Data acquisition
TSSOP package and a 32-lead LFCSP package.
Strain gage transducers
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND DVDD DGND
REFIN1(+) REFIN1(–)
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AINCOM
BPDSW
AD7193
AGND
MUX
PGA
Σ-Δ
ADC
TEMP
SENSOR
CLOCK
CIRCUITRY
MCLK1 MCLK2
Figure 1.
SERIAL
INTERFACE
AND
CONTROL
LOGIC
DOUT/RDY
DIN
SCLK
CS
SYNC
P3
P2
P0/REFIN2(–) P1/REFIN2(+)
Rev. E
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AD7193 Datasheet
AD7193
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Timing Characteristics ................................................................ 8
Absolute Maximum Ratings.......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution................................................................................ 10
Pin Configurations and Function Descriptions ......................... 11
Typical Performance Characteristics ........................................... 15
RMS Noise and Resolution............................................................ 18
Sinc4 Chop Disabled................................................................... 18
Sinc3 Chop Disabled................................................................... 19
Fast Settling ................................................................................. 20
On-Chip Registers .......................................................................... 21
Communications Register......................................................... 22
Status Register............................................................................. 23
Mode Register ............................................................................. 24
Configuration Register .............................................................. 27
Data Register ............................................................................... 29
ID Register................................................................................... 29
GPOCON Register..................................................................... 29
Offset Register............................................................................. 30
Full-Scale Register ...................................................................... 30
ADC Circuit Information.............................................................. 31
Overview...................................................................................... 31
Analog Input Channel ............................................................... 32
Programmable Gain Array (PGA) ........................................... 32
Data Sheet
Reference ..................................................................................... 32
Reference Detect......................................................................... 33
Bipolar/Unipolar Configuration .............................................. 33
Data Output Coding .................................................................. 33
Burnout Currents ....................................................................... 33
Channel Sequencer .................................................................... 33
Digital Interface .......................................................................... 34
Reset ............................................................................................. 38
System Synchronization ............................................................ 38
Enable Parity ............................................................................... 38
Clock ............................................................................................ 38
Bridge Power-Down Switch ...................................................... 38
Temperature Sensor ................................................................... 39
Logic Outputs ............................................................................. 39
Calibration................................................................................... 39
Digital Filter .................................................................................... 41
Sinc4 Filter (Chop Disabled) ..................................................... 41
Sinc3 Filter (Chop Disabled) ..................................................... 43
Chop Enabled (Sinc4 Filter) ...................................................... 45
Chop Enabled (Sinc3 Filter) ...................................................... 47
Fast Settling Mode (Sinc4 Filter)............................................... 48
Fast Settling Mode (Sinc3 Filter)............................................... 50
Fast Settling Mode (Chop Enabled)......................................... 51
Summary of Filter Options ....................................................... 52
Grounding and Layout .................................................................. 53
Applications Information .............................................................. 54
Flowmeter.................................................................................... 54
Outline Dimensions ....................................................................... 55
Ordering Guide .......................................................................... 55
Rev. E | Page 2 of 56


Features Datasheet pdf Data Sheet 4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA AD7193 FEATURES Pressure measurement Fast settling filter option 4 differe ntial/8 pseudo differential input chann els RMS noise: 11 nV @ 4.7 Hz (gain = 1 28) 15.5 noise-free bits @ 2.4 kHz (gai n = 128) Up to 22 noise-free bits (gain = 1) Temperature measurement Flow mea surement Weigh scales Chromatography Me dical and scientific instrumentation O ffset drift: ±5 nV/°C Gain drift: ±1 ppm/°C Specified drift over time Auto matic channel sequencer Programmable ga in (1 to 128) Output data rate: 4.7 Hz to 4.8 kHz Internal or external clock GENERAL DESCRIPTION The AD7193 is a low noise, complete analog front end for h igh precision measurement applications. It contains a low noise, 24-bit sigma- delta (Σ-Δ) analog-to-digital convert er (ADC). The on-chip low noise gain st age means that signals of small amplitu de can interface directly to the ADC. Simultaneous 50 Hz/60 Hz rejection The device can be configured to h.
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