Document
CY28510
Peripheral I/O Clock Generator
Features
• 15 33.27 MHz or 66.669-MHz clock outputs • 1 REF 14.318 MHz • Divide by 2, spread spectrum and output enable all selectable on a per-output basis via I2C register bits • Divide by 2 mode default values strappable on a per-group basis • Output Enable pin controls all outputs • I2C Compatible Programmability With Block and Byte Modes • I2C Operates Up to 1MHz • I2C Address Selection of D0, D2, D4 or D6 • 48-Pin SSOP Package
Block Diagram
XIN REF
Pin Configuration
Mux Mux PLL 1with Spread Spectrum Mux
y2 y2 y2 y2 y2 y2 y2 y2 y2 y2 y2 y2 y2 y2 y2
CLKG0_0 CLKG0_1 CLKG0_2 CLKG0_3 CLKG0_4 CLKG0_5 CLKG0_6 CLKG0_7 CLKG1_0 CLKG1_1 CLKG1_2 CLKG1_3 CLKG2_0 CLKG2_1 CLKG3
66MHz
Mux Mux Mux Mux (Group Frequency Select, 33 or 66MHz) Mux
CLK_STOP#
PLL 2 no Spread Spectrum
66MHz
GFS0
Mux
SCLK www.DataSheet4U.com I2C SDATA ADDSEL(0:1)
Mux Mux Mux
GFS3 REF GFS0 VDDX VSSX XIN XOUT VDDC ADDSEL0 ADDSEL1 VSSC CLK_STOP# SCLK SDATA GFS1 GFS2 OE CLKG3 VDDQ3 VSSQ3 VSSQ2 CLKG2_1 CLKG2_0 VDDQ2
GFS1
Mux
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VDDQ0 CLKG0_0 CLKG0_1 VSSQ0 CLKG0_2 VDDQ0 VSSQ0 CLKG0_3 CLKG0_4 VDDQ0 CLKG0_5 CLKG0_6 CLKG0_7 VSSQ0 VDDQ1 CLKG1_0 CLKG1_1 VSSQ1 VDDQ1 CLKG1_2 CLKG1_3 VSSQ1 VDDA VSSA
CY28510
Mux
GFS2
Mux
GFS3
OE
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 12
www.SpectraLinear.com
CY28510
Pin Description
Pin
2 6
Name
REF XIN
Type
O I
Power
VDDX VDDX
Description
Reference Clock: 3.3V 14.318-MHz clock output. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection for an external 14.318-MHz crystal output. I2C address selection. ADDSEL1, ADSEL0: 0,0 = D0; 0,1 = D2, 1,0 = D4, 1,1 = D6
7 9 10 12 13 14 3 15 16 1 17 18 22,23 28,29,32,33 36,37,38,40,4 1,44,46,47 39 43 48 www.DataSheet4U.com 35 42 45 30 37 34 31 24 21 19 20 26 25 4 5 8
XOUT ADDSEL0 ADDSEL1 CLK_STOP# SCLK SDATA GFS0 GFS1 GFS2 GFS3 OE CLKG3 CLKG2_(1:0) CLKG1_(3:0) CLKG0_(7:0) VDDQ0_2 VDDQ0_1 VDDQ0_0 VSSQ0 VSSQ0 VSSQ0 VDDQ1 VSSQ1 VDDQ1 VSSQ1 VDDQ2 VSSQ2 VDDQ3 VSSQ3 VDDA VSSA VDDX VSSX VDDC
O I, PU 250 K: I, PU 250 K: I, PU 250 K: I I/O I, PD 250 K: I, PD 250 K: I, PD 250 K: I, PD 250 K: I, PU 250 K: O O O O PWR PWR PWR GND GND GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR
VDDX VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VSSQ3 VSSQ2 VSSQ1 VSSQ0
Synchronous clock stop pin. When low, all of the clocks except REF are stopped low after completing a normal positive pulse cycle. I2C compatible SCLOCK. I2C compatible SDATA. Group frequency select 0. 0 = 33 MHz, 1 = 66 MHz. Group frequency select 1. 0 = 33 MHz, 1 = 66 MHz. Group frequency select 2. 0 = 33 MHz, 1 = 66 MHz. Group frequency select 3. 0 = 33 MHz, 1 = 66 MHz. Output enable. 1 = enabled, 0 = disabled (tri-state) Output clock, group 3, 33 or 66 MHz. Output clocks, group 2, 33 or 66 MHz. Output clocks, group 1, 33 or 66 MHz. Output clocks, group 0, 33 or 66 MHz. 3.3V Power supply for outputs CLKG0_(7:6). 3.3V Power supply for outputs CLKG0_(5:3). 3.3V Power supply for outputs CLKG0_(2:0). Ground for output buffers CLKG0_(7:6). Ground for output buffers CLKG0_(5:3). Ground for output buffers CLKG0_(2:0). 3.3V Power supply for outputs CLKG1_(3:2). Ground for output buffers CLKG1_(3:2). 3.3V Power supply for outputs CLKG1_(1:0). Ground for output buffers CLKG1_(1:0). 3.3V Power supply for outputs CLKG2_(1:0). Ground for output buffers. 3.3V Power supply for outputs. Ground for output buffers. 3.3V Power supply for analog PLLs. Ground for analog PLLs. 3.3V Power supply for oscillator. Ground for oscillator. 3.3V Power supply for core.
11
VSSC
GND
Ground for core.
Rev 1.0, November 20, 2006
Page 2 of 12
CY28510
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, yet the interface is available at any time except power-down.
Data Protocol
The clock driver serial protocol accepts Byte Write, Byte Read, Block Write, and Block Read operation from the controller. For Block Write/Read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For Byte Write and Byte Read operations, the system controller can access individual index.