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CY7C1143V18 Datasheet, Equivalent, Burst Architecture.(CY7C11xxV18) SRAM 4-Word Burst Architecture (CY7C11xxV18) SRAM 4-Word Burst Architecture |
| Part | CY7C1143V18 |
|---|---|
| Description | (CY7C11xxV18) SRAM 4-Word Burst Architecture |
| Feature | CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C 1145V18
18-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2. 0 Cycle Read Lat ency) Features Separate Independent rea d and write data ports ❐ Supports con current transactions ■ 300 MHz to 375 MHz clock for high bandwidth ■ 4-Wor d Burst for reducing address bus freque ncy ■ Double Data Rate (DDR) interfac es on both read and write ports (data t ransferred at 750 MHz) at 375 MHz ■ R ead latency of 2. 0 clock cycles ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Echo clocks (CQ and CQ) simplify d ata capture in high speed system . |
| Manufacture | Cypress Semiconductor |
| Datasheet |
| Part | CY7C1143V18 |
|---|---|
| Description | (CY7C11xxV18) SRAM 4-Word Burst Architecture |
| Feature | CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C 1145V18
18-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2. 0 Cycle Read Lat ency) Features Separate Independent rea d and write data ports ❐ Supports con current transactions ■ 300 MHz to 375 MHz clock for high bandwidth ■ 4-Wor d Burst for reducing address bus freque ncy ■ Double Data Rate (DDR) interfac es on both read and write ports (data t ransferred at 750 MHz) at 375 MHz ■ R ead latency of 2. 0 clock cycles ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Echo clocks (CQ and CQ) simplify d ata capture in high speed system . |
| Manufacture | Cypress Semiconductor |
| Datasheet |
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