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CY7C1148V18 Datasheet, Equivalent, Burst Architecture.

(CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture

(CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture

 

 

 

Part CY7C1148V18
Description (CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
Feature CY7C1146V18 CY7C1157V18 CY7C1148V18 CY7C 1150V18 18-Mbit DDR-II+ SRAM 2-Word Bu rst Architecture (2.
0 Cycle Read Latenc y) Features ■ ■ ■ ■ ■ ■ Fu nctional Description The CY7C1146V18, C Y7C1157V18, CY7C1148V18, and CY7C1150V1 8 are 1.
8V Synchronous Pipelined SRAMs equipped with DDR-II+ architecture.
The DDR-II+ consists of an SRAM core with advanced synchronous peripheral circuit ry.
Addresses for read and write are la tched on alternate rising edges of the input (K) clock.
Write data is register ed on the rising edges of both K and K.
Read data is driven on the rising edge s of K and K.
Each address .
Manufacture Cypress Semiconductor
Datasheet
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Part CY7C1148V18
Description (CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
Feature CY7C1146V18 CY7C1157V18 CY7C1148V18 CY7C 1150V18 18-Mbit DDR-II+ SRAM 2-Word Bu rst Architecture (2.
0 Cycle Read Latenc y) Features ■ ■ ■ ■ ■ ■ Fu nctional Description The CY7C1146V18, C Y7C1157V18, CY7C1148V18, and CY7C1150V1 8 are 1.
8V Synchronous Pipelined SRAMs equipped with DDR-II+ architecture.
The DDR-II+ consists of an SRAM core with advanced synchronous peripheral circuit ry.
Addresses for read and write are la tched on alternate rising edges of the input (K) clock.
Write data is register ed on the rising edges of both K and K.
Read data is driven on the rising edge s of K and K.
Each address .
Manufacture Cypress Semiconductor
Datasheet
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CY7C1148V18

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