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CY7C1148V18 Dataheets PDF



Part Number CY7C1148V18
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description (CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
Datasheet CY7C1148V18 DatasheetCY7C1148V18 Datasheet (PDF)

CY7C1146V18 CY7C1157V18 CY7C1148V18 CY7C1150V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features ■ ■ ■ ■ ■ ■ Functional Description The CY7C1146V18, CY7C1157V18, CY7C1148V18, and CY7C1150V18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II+ architecture. The DDR-II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered o.

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CY7C1146V18 CY7C1157V18 CY7C1148V18 CY7C1150V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features ■ ■ ■ ■ ■ ■ Functional Description The CY7C1146V18, CY7C1157V18, CY7C1148V18, and CY7C1150V18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II+ architecture. The DDR-II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 8-bit words (CY7C1146V18) or 9-bit words (CY7C1157V18) or 18-bit words (CY7C1148V18) or 36-bit words (CY7C1150V18) that burst sequentially into or out of the device. Asynchronous inputs include output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. 18 Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) 300 MHz to 375 MHz clock for high bandwidth 2-Word burst for reducing address bus frequency Double Data Rate (DDR) interfaces (data transferred at 750 MHz) @ 375 MHz Read latency of 2.0 clock cycles Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only Echo clocks (CQ and CQ) simplify data capture in high-speed systems Data valid pin (QVLD) to indicate valid data on the output Synchronous internally self-timed writes Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD[1] ■ ■ ■ ■ ■ HSTL inputs and Variable drive HSTL output buffers ■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm) ■ Offered in both Pb-free and non Pb-free packages ■ ■ JTAG 1149.1-compatible test access port Delay Lock Loop (DLL) for accurate data placement Configurations With Read Cycle Latency of 2.0 cycles: CY7C1146V18 – 2M x 8 www.DataSheet4U.com CY7C1157V18 – 2M x 9 CY7C1148V18 – 1M x 18 CY7C1150V18 – 512K x 36 Selection Guide 375 MHz Maximum Operating Frequency Maximum Operating Current 375 1020 333 MHz 333 920 300 MHz 300 850 Unit MHz mA Note 1. The QDR consortium specification for VDDQ is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting VDDQ = 1.4V to VDD. Cypress Semiconductor Corporation Document Number: 001-06621 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 21, 2007 CY7C1146V18 CY7C1157V18 CY7C1148V18 CY7C1150V18 Logic Block Diagram (CY7C1146V18) A(19:0) 20 Write Add. Decode LD K K DOFF Read Add. Decode Address Register Write Reg 1M x 8 Array Write Reg 1M x 8 Array 8 Output Logic Control CLK Gen. R/W Read Data Reg. 16 Control Logic CQ CQ 8 Reg. 8 DQ[7:0] QVLD VREF R/W NWS[1:0] 8 8 Reg. Reg. 8 Logic Block Diagram (CY7C1157V18) www.DataSheet4U.com A(19:0) 20 Write Add. Decode LD K K DOFF Read Add. Decode Address Register Write Reg 1M x 9 Array Write Reg 1M x 9 Array 9 Output Logic Control CLK Gen. R/W Read Data Reg. 18 Control Logic CQ CQ 9 Reg. 9 DQ[8:0] QVLD VREF R/W BWS[0] 9 9 Reg. Reg. 9 Document Number: 001-06621 Rev. *C Page 2 of 27 CY7C1146V18 CY7C1157V18 CY7C1148V18 CY7C1150V18 Logic Block Diagram (CY7C1148V18) A(18:0) 19 Write Add. Decode LD K K DOFF Read Add. Decode Address Register Write Reg 512K x 18 Array Write Reg 512K x 18 Array 18 Output Logic Control CLK Gen. R/W Read Data Reg. 36 Control Logic 18 18 Reg. Reg. Reg. 18 18 18 CQ CQ DQ[17:0] QVLD VREF R/W BWS[1:0] Logic Block Diagram (CY7C1150V18) www.DataSheet4U.com A(17:0) 18 Write Add. Decode LD K K DOFF Read Add. Decode Address Register Write Reg 256K x 36 Array Write Reg 256K x 36 Array 36 Output Logic Control CLK Gen. R/W Read Data Reg. 72 Control Logic 36 36 Reg. Reg. Reg. 36 36 36 CQ CQ DQ[35:0] QVLD VREF R/W BWS[3:0] Document Number: 001-06621 Rev. *C Page 3 of 27 CY7C1146V18 CY7C1157V18 CY7C1148V18 CY7C1150V18 Pin Configurations 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1146V18 (2M x 8) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/72M NC NC NC NC NC NC VREF NC NC DQ6 NC NC NC TCK 3 A NC NC NC DQ4 NC DQ5 VDDQ NC NC NC NC NC DQ7 A 4 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 NWS1 NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A QVLD NC 7 NC/144M NWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 NC/36M NC NC NC NC NC NC VREF DQ1 NC NC NC NC NC TMS 1.


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