HY5DU281622FTP

128Mb DDR SDRAM HY5DU281622FTP www.DataSheet4U.com This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.03 /Jun. 2006 1 HY5DU281622FT(P) Series Revision History Revision No. 0.01 0.02 0.03 First version for internal review State Diagram modified Defined : IDD value History Draft Date Feb. 2006 Apr. 2006 Apr. 2006 Remark www.DataSheet4U.com Rev. 0.03 /Jun. 2006 2 HY5DU281622FT(P) Series DESCRIPTION The HY5DU281622FT(P) is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. This Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. FEATURES VDD, VDDQ = 2.3V min ~ 2.7V max (Typical 2.5V Operation +/- 0.2V for DDR266, 333) VDD, VDDQ = 2.4V min ~ 2.7V max (Typical 2.6V Operation +0.1/- 0.2V for DDR400 and 400Mbps/pin product) All inputs and outputs are compatible with SSTL_2 int...