+ 32-Mbit/64-Mbit. AT52SC1284J Datasheet

AT52SC1284J Datasheet PDF, Equivalent


Part Number

AT52SC1284J

Description

(AT52SC1283J / AT52SC1284J) 128-Mbit Flash + 32-Mbit/64-Mbit

Manufacture

ATMEL Corporation

Total Page 30 Pages
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Download AT52SC1284J Datasheet


AT52SC1284J Datasheet
Module Features
128-Mbit Burst/Page Flash + 32-Mbit/64-Mbit PSRAM
Single 88-ball (8 mm x 10 mm x 1.2 mm) CBGA Package
1.7V to 1.95V VCC
1.8V to 1.95V for VCCQ and PVCC
128-Mbit Flash Features
8M x 16 Organization
High Performance
– Random Access Time – 70 ns, 85 ns
– Page Mode Read Time – 20 ns
– Synchronous Burst Frequency – 66 MHz
– Configurable Burst Operation
Sector Erase Architecture
– Sixteen 4K Word Sectors with Individual Write Lockout
– Two Hundred Fifty-four 32K Word Main Sectors with Individual Write Lockout
Typical Sector Erase Time: 32K Word Sectors – 800 ms; 4K Word Sectors – 200 ms
Thirty-two Plane Organization, Permitting Concurrent Read in Any of the Thirty-one
Planes not Being Programmed/Erased
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 30 mA Active
– 20 µA Standby
VPP Pin for Write Protection and Accelerated Program Operations
RESET Input for Device Initialization
Two Protection Registers (128 Bits + 2,048 Bits)
Common Flash Interface (CFI)
wwwT.DoaptaaSnhdeeBt4oUt.tcoomm Boot Sectors
1.7V to 1.95V Operating Voltage
Asynchronous/Page PSRAM Features
32-Mbit (2M Word x 16)/64-Mbit (4M Word x 16)
70 ns Random Access Time
30 ns Page Read Cycle Time
1.8V to 1.95V Operating Voltage
<10 µA Deep Standby Power
128-Mbit Flash
+ 32-Mbit/64-Mbit
PSRAM
Stack Memory
AT52SC1283J
AT52SC1284J
Preliminary
Stack Module Memory Contents
Device
AT52SC1283J
AT52SC1284J
Memory Combination
128M Flash + 32M PSRAM
128M Flash + 64M PSRAM
3530B–STKD–2/4/05

AT52SC1284J Datasheet
1. Memory Module Description
The AT52SC1283J/1284J memory module offers 128-megabit of nonvolatile Flash
memory along with 32M/64M of PSRAM memory. The combined memory is packaged in a sin-
gle 8 x 10 x 1.2 mm CBGA package with 88 balls.
The Flash memory provides Asynchronous, Page and Burst Mode Read operation for the most
optimum system performance.
The 32M/64M PSRAM is based on 1T/1C cell technology and offers interface compatibility with
SRAM. The device supports Asynchronous and Page mode operations.
2. Block Diagram
www.DataSheet4U.com
CE1
OE1
WE
AVD
CLK
RST
WP
VPP
WAIT
VCCQ
VCC
PCS1
ZZ
POE
PWE
PLB
PUB
PVCC
CE1
OE1
WE
AVD
CLK
RST
WP
VPP
WAIT
VCCQ
VCC
I/O0 - I/O15
128M Flash
A0 - A22
PCS1
ZZ
POE
PWE
PLB
PUB
VCCQ
PVCC 32M/64M PSRAM
I/O0 - I/O15
A0 - A20
A21 (64M)
I/O0 - I/O15
A0 - A22
2 AT52SC1283J/1284J [Preliminary]
3530B–STKD–2/4/05


Features Datasheet pdf Module Features • • • • 128-Mbit Burst/Page Flash + 32-Mbit/64-Mbit PSR AM Single 88-ball (8 mm x 10 mm x 1.2 m m) CBGA Package 1.7V to 1.95V VCC 1.8V to 1.95V for VCCQ and PVCC 128-Mbit Fl ash Features • 8M x 16 Organization High Performance – Random Access T ime – 70 ns, 85 ns – Page Mode Read Time – 20 ns – Synchronous Burst F requency – 66 MHz – Configurable Bu rst Operation • Sector Erase Architec ture – Sixteen 4K Word Sectors with I ndividual Write Lockout – Two Hundred Fifty-four 32K Word Main Sectors with Individual Write Lockout • Typical Se ctor Erase Time: 32K Word Sectors – 8 00 ms; 4K Word Sectors – 200 ms • T hirty-two Plane Organization, Permittin g Concurrent Read in Any of the Thirty- one Planes not Being Programmed/Erased • Suspend/Resume Feature for Erase an d Program – Supports Reading and Prog ramming Data from Any Sector by Suspend ing Erase of a Different Sector – Sup ports Reading Any Word by Suspending Programming of Any Other Word • Low-power Operation – 30 mA Active – 20 .
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