D5108AFTA-5B-E EDD5108AFTA-5B-E Datasheet

D5108AFTA-5B-E Datasheet PDF, Equivalent


Part Number

D5108AFTA-5B-E

Description

EDD5108AFTA-5B-E

Manufacture

Elpida Memory

Total Page 30 Pages
PDF Download
Download D5108AFTA-5B-E Datasheet PDF


D5108AFTA-5B-E
DATA SHEET
512M bits DDR SDRAM
EDD5108AFTA (64M words × 8 bits)
EDD5116AFTA (32M words × 16 bits)
Specifications
Density: 512M bits
Organization
16M words × 8 bits × 4 banks (EDD5108AFTA)
8M words × 16 bits × 4 banks (EDD5116AFTA)
Package: 66-pin plastic TSOP (II)
Lead-free (RoHS compliant)
Power supply:
DDR400:
VDD, VDDQ = 2.6V ± 0.1V
DDR333, 266: VDD, VDDQ = 2.5V ± 0.2V
Data rate: 400Mbps/333Mbps/266Mbps (max.)
Four internal banks for concurrent operation
Interface: SSTL_2
Burst lengths (BL): 2, 4, 8
Burst type (BT):
Sequential (2, 4, 8)
Interleave (2, 4, 8)
/CAS Latency (CL): 2, 2.5, 3
Precharge: auto precharge option for each burst
access
Driver strength: normal/weak
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period: 7.8μs
Operating ambient temperature range
www.DataSheeTt4AU=.co0m°C to +70°C
Features
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
Data inputs, outputs, and DM are synchronized with
DQS
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Document No. E0699E50 (Ver. 5.0)
Date Published November 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2005-2006

D5108AFTA-5B-E
EDD5108AFTA, EDD5116AFTA
Ordering Information
Part number
EDD5108AFTA-5B-E
EDD5108AFTA-5C-E
EDD5108AFTA-6B-E
EDD5108AFTA-7A-E
EDD5108AFTA-7B-E
EDD5116AFTA-5B-E
EDD5116AFTA-5C-E
EDD5116AFTA-6B-E
EDD5116AFTA-7A-E
EDD5116AFTA-7B-E
Mask
version
F
Organization
(words × bits)
64M × 8
Internal
banks
4
Data rate
Mbps (max.)
400
333
266
32M × 16
400
333
266
JEDEC speed bin
(CL-tRCD-tRP)
DDR400B (3-3-3)
DDR400C (3-4-4)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR400B (3-3-3)
DDR400C (3-4-4)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
Package
66-pin Plastic
TSOP (II)
Part Number
E D D 51 08 A F TA - 5B - E
Elpida Memory
Type
D: Monolithic Device
Product Family
D: DDR SDRAM
Density / Bank
51: 512M / 4-bank
Organization
08: x8
16: x16
Power Supply, Interface
A: 2.5V, SSTL_2
Speed Grade Compatibility
Speed bin
www.DataSDhDeeRt440U0.Bcom
DDR400C
DDR333B
DDR266A
DDR266B
Operating Frequencies
CL2
133MHz
133MHz
133MHz
133MHz
100MHz
CL2.5
166MHz
166MHz
166MHz
133MHz
133MHz
Environment Code
E: Lead Free
(RoHS compliant)
Speed
5B: DDR400B (3-3-3)
5C: DDR400C (3-4-4)
6B: DDR333B (2.5-3-3)
7A: DDR266A (2-3-3)
7B: DDR266B (2.5-3-3)
Package
TA: TSOP (II)
Die Rev.
CL3
200MHz
200MHz
166MHz
133MHz
133MHz
Data Sheet E0699E50 (Ver. 5.0)
2


Features DATA SHEET 512M bits DDR SDRAM EDD5108A FTA (64M words × 8 bits) EDD5116AFTA ( 32M words × 16 bits) Specifications Density: 512M bits • Organization 16M words × 8 bits × 4 banks (EDD5 108AFTA) ⎯ 8M words × 16 bits × 4 b anks (EDD5116AFTA) • Package: 66-pin plastic TSOP (II) ⎯ Lead-free (RoHS c ompliant) • Power supply: ⎯ DDR400: VDD, VDDQ = 2.6V ± 0.1V ⎯ DDR333, 2 66: VDD, VDDQ = 2.5V ± 0.2V • Data r ate: 400Mbps/333Mbps/266Mbps (max.) • Four internal banks for concurrent ope ration • Interface: SSTL_2 • Burst lengths (BL): 2, 4, 8 • Burst type (B T): ⎯ Sequential (2, 4, 8) ⎯ Interl eave (2, 4, 8) • /CAS Latency (CL): 2 , 2.5, 3 • Precharge: auto precharge option for each burst access • Driver strength: normal/weak • Refresh: aut o-refresh, self-refresh • Refresh cyc les: 8192 cycles/64ms ⎯ Average refre sh period: 7.8μs • Operating ambient temperature range www.DataSheet4U.com ⎯ TA = 0°C to +70°C Features • Double-data-rate architecture; two data transfers per clock cycle • The high-speed dat.
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