EDD5104ADTA-E SDRAM Datasheet

EDD5104ADTA-E Datasheet PDF, Equivalent


Part Number

EDD5104ADTA-E

Description

512M bits DDR SDRAM

Manufacture

Elpida Memory

Total Page 30 Pages
PDF Download
Download EDD5104ADTA-E Datasheet PDF


EDD5104ADTA-E
PRELIMINARY DATA SHEET
512M bits DDR SDRAM
EDD5104ADTA-E (128M words × 4 bits)
EDD5108ADTA-E (64M words × 8 bits)
EDD5116ADTA-E (32M words × 16 bits)
Description
The EDD5104AD, the EDD5108AD and the
EDD5116AD are 512M bits Double Data Rate (DDR)
SDRAM. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 2 bits prefetch-
pipelined architecture. Data strobe (DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. It is packaged in standard 66-pin
plastic TSOP (II).
Features
Power supply: VDD, VDDQ = 2.5V ± 0.2V
Data Rate: 333Mbps/266Mbps (max.)
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs, outputs, and DM are synchronized with
DQS
4 internal banks for concurrent operation
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
www.DataSheDetif4fUer.ceonmtial clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Auto precharge option for each burst access
SSTL_2 compatible I/O
Programmable burst length (BL): 2, 4, 8
Programmable /CAS latency (CL): 2, 2.5
Programmable output driver strength: normal/weak
Refresh cycles: 8192 refresh cycles/64ms
7.8µs maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
TSOP (II) package with lead free solder (Sn-Bi)
Document No. E0501E10 (Ver. 1.0)
Date Published March 2004 (K) Japan
URL: http://www.elpida.com
Pin Configurations
/xxx indicates active low signal.
VDD VDD VDD
NC DQ0 DQ0
VDDQ VDDQ VDDQ
NC NC DQ1
DQ0 DQ1 DQ2
VSSQ VSSQ VSSQ
NC NC DQ3
NC DQ2 DQ4
VDDQ VDDQ VDDQ
NC NC DQ5
DQ1 DQ3 DQ6
VSSQ VSSQ VSSQ
NC NC DQ7
NC NC NC
VDDQ VDDQ VDDQ
NC NC LDQS
NC NC NC
VDD VDD VDD
NC NC NC
NC NC LDM
/WE /WE /WE
/CAS /CAS /CAS
/RAS /RAS /RAS
/CS /CS /CS
NC NC NC
BA0 BA0 BA0
BA1 BA1 BA1
A10(AP) A10(AP) A10(AP)
A0 A0 A0
A1 A1 A1
A2 A2 A2
A3 A3 A3
VDD VDD VDD
66-pin Plastic TSOP(II)
1 66
2 65
3 64
4 63
5 62
6 61
7 60
8 59
9 58
10 57
11 56
12 55
13 54
14 53
15 52
16 51
17 50
18 49
19 48
20 47
21 46
22 45
23 44
24 43
25 42
26 41
27 40
28 39
29 38
30 37
31 36
32 35
33 34
VSS VSS VSS
DQ15 DQ7 NC
VSSQ VSSQ VSSQ
DQ14 NC NC
DQ13 DQ6 DQ3
VDDQ VDDQ VDDQ
DQ12 NC NC
DQ11 DQ5 NC
VSSQ VSSQ VSSQ
DQ10 NC NC
DQ9 DQ4 DQ2
VDDQ VDDQ VDDQ
DQ8 NC NC
NC NC NC
VSSQ VSSQ VSSQ
UDQS DQS DQS
NC NC NC
VREF VREF VREF
VSS VSS VSS
UDM DM DM
/CK /CK /CK
CK CK CK
CKE CKE CKE
NC NC NC
A12 A12 A12
A11 A11 A11
A9 A9 A9
A8 A8 A8
A7 A7 A7
A6 A6 A6
A5 A5 A5
A4 A4 A4
VSS VSS VSS
X 16
X8
X4
A0 to A12
BA0, BA1
DQ0 to DQ15
DQS, LDQS, UDQS
/CS
/RAS
/CAS
/WE
DM, LDM, UDM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
(Top view)
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Elpida Memory, Inc. 2004

EDD5104ADTA-E
EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E
Ordering Information
Part number
EDD5104ADTA-6B-E
EDD5104ADTA-7A-E
EDD5104ADTA-7B-E
EDD5108ADTA-6B-E
EDD5108ADTA-7A-E
EDD5108ADTA-7B-E
EDD5116ADTA-6B-E
EDD5116ADTA-7A-E
EDD5116ADTA-7B-E
EDD5104ADTA-6BL-E
EDD5104ADTA-7AL-E
EDD5104ADTA-7BL-E
EDD5108ADTA-6BL-E
EDD5108ADTA-7AL-E
EDD5108ADTA-7BL-E
EDD5116ADTA-6BL-E
EDD5116ADTA-7AL-E
EDD5116ADTA-7BL-E
Mask
version
D
D
Organization
(words × bits)
128M × 4
64M × 8
32M × 16
128M × 4
64M × 8
32M × 16
Internal
banks
4
4
Data rate
Mbps (max.)
333
266
266
333
266
266
333
266
266
333
266
266
333
266
266
333
266
266
JEDEC speed bin
(CL-tRCD-tRP)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
Package
66-pin Plastic
TSOP (II)
Part Number
E D D 51 04 A D TA - 6B L - E
Elpida Memory
Type
D: Monolithic Device
Product Code
D: DDR SDRAM
Density / Bank
51: 512M / 4-bank
Bit Organization
04: x4
08: x8
16: x16
www.DataShVeoeltat4gUe,.cInotmerface
A: 2.5V, SSTL_2
Environment Code
E: Lead Free
Power Consumption
Blank: Normal
L: Low Power
Package
TA: TSOP (II)
Die Rev.
Speed
6B: DDR333B (2.5-3-3)
7A: DDR266A (2-3-3)
7B: DDR266B (2.5-3-3)
Preliminary Data Sheet E0501E10 (Ver. 1.0)
2


Features PRELIMINARY DATA SHEET 512M bits DDR SD RAM EDD5104ADTA-E (128M words × 4 bits ) EDD5108ADTA-E (64M words × 8 bits) E DD5116ADTA-E (32M words × 16 bits) Des cription The EDD5104AD, the EDD5108AD a nd the EDD5116AD are 512M bits Double D ata Rate (DDR) SDRAM. Read and write op erations are performed at the cross poi nts of the CK and the /CK. This highspe ed data transfer is realized by the 2 b its prefetchpipelined architecture. Dat a strobe (DQS) both for read and write are available for high speed and reliab le data bus design. By setting extended mode register, the on-chip Delay Locke d Loop (DLL) can be set enable or disab le. It is packaged in standard 66-pin p lastic TSOP (II). Pin Configurations / xxx indicates active low signal. 66-pin Plastic TSOP(II) VDD VDD VDD NC DQ0 DQ 0 VDDQ VDDQ VDDQ NC NC DQ1 DQ0 DQ1 DQ2 VSSQ VSSQ VSSQ NC NC DQ3 NC DQ2 DQ4 VDD Q VDDQ VDDQ NC NC DQ5 DQ1 DQ3 DQ6 VSSQ VSSQ VSSQ NC NC DQ7 NC NC NC VDDQ VDDQ VDDQ NC NC LDQS NC NC NC VDD VDD VDD NC NC NC NC NC LDM /WE /WE /W.
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