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EDD5108AFTA-5 Datasheet, Equivalent, DDR SDRAM.512M bits DDR SDRAM 512M bits DDR SDRAM |
| Part | EDD5108AFTA-5 |
|---|---|
| Description | 512M bits DDR SDRAM |
| Feature | DATA SHEET
512M bits DDR SDRAM
EDD5108A FTA-5 (64M words × 8 bits, DDR400) EDD 5116AFTA-5 (32M words × 16 bits, DDR40 0)
Description
The EDD5108AFTA and the EDD5116AFTA are 512M bits Double Data R ate (DDR) SDRAM organized as 16,777,216 words × 8 bits × 4 banks and 8,388,6 08 words × 16 bits × 4 banks, respect ively. Read and write operations are pe rformed at the cross points of the CK a nd the /CK. This high-speed data transf er is realized by the 2 bits prefetch-p ipelined architecture. Data strobe (DQS ) both for read and write are available for high speed and reliable data bus d esign. By setting ex . |
| Manufacture | Elpida Memory |
| Datasheet |
| Part | EDD5108AFTA-5 |
|---|---|
| Description | 512M bits DDR SDRAM |
| Feature | DATA SHEET
512M bits DDR SDRAM
EDD5108A FTA-5 (64M words × 8 bits, DDR400) EDD 5116AFTA-5 (32M words × 16 bits, DDR40 0)
Description
The EDD5108AFTA and the EDD5116AFTA are 512M bits Double Data R ate (DDR) SDRAM organized as 16,777,216 words × 8 bits × 4 banks and 8,388,6 08 words × 16 bits × 4 banks, respect ively. Read and write operations are pe rformed at the cross points of the CK a nd the /CK. This high-speed data transf er is realized by the 2 bits prefetch-p ipelined architecture. Data strobe (DQS ) both for read and write are available for high speed and reliable data bus d esign. By setting ex . |
| Manufacture | Elpida Memory |
| Datasheet |
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