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ADC10D1500 Dataheets PDF



Part Number ADC10D1500
Manufacturers National Semiconductor Corporation
Logo National Semiconductor Corporation
Description Dual 1.0/1.5 GSPS Or Single 2.0/3.0 GSPS ADC
Datasheet ADC10D1500 DatasheetADC10D1500 Datasheet (PDF)

ADC10D1000/1500 Low Power, 10-Bit, Dual 1.0/1.5 GSPS or Single 2.0/3.0 GSPS ADC November 19, 2009 ADC10D1000/ADC10D1500 Low Power, 10-Bit, Dual 1.0/1.5 GSPS or Single 2.0/3.0 GSPS ADC 1.0 General Description The ADC10D1000/1500 is the latest advance in National's Ultra-High-Speed ADC family. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution for dual channels at sampling rates of up to 1.0/1.5 GSPS (Non-DES Mode) or for a single channel up .

  ADC10D1500   ADC10D1500


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ADC10D1000/1500 Low Power, 10-Bit, Dual 1.0/1.5 GSPS or Single 2.0/3.0 GSPS ADC November 19, 2009 ADC10D1000/ADC10D1500 Low Power, 10-Bit, Dual 1.0/1.5 GSPS or Single 2.0/3.0 GSPS ADC 1.0 General Description The ADC10D1000/1500 is the latest advance in National's Ultra-High-Speed ADC family. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution for dual channels at sampling rates of up to 1.0/1.5 GSPS (Non-DES Mode) or for a single channel up to 2.0/3.0 GSPS (DES Mode). The ADC10D1000/1500 achieves excellent accuracy and dynamic performance while dissipating less than 2.8/3.6 Watts. The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C. The ADC10D1000/1500 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. An expanded feature set includes AutoSync for multi-chip synchronization, 15-bit programmable gain and 12-bit plus sign programmable offset adjustment for each channel. The improved internal track-and-hold amplifier and the extended self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing 9.1/9.0 Effective Number of Bits (ENOB) with a 100 MHz input signal and a 1.0/1.5 GHz sample rate while providing a 10-18 Code Error Rate (CER) Dissipating a typical 2.77/3.59 Watts in Non-Demultiplex Mode at 1.0/1.5 GSPS from a single 1.9V supply, this device is guaranteed to have no missing codes over the full operating temperature range. Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demux Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such www.DataSheet4U.com that the output data rate is sent out two times slower to relax data-capture timing requirements. The part can also be used as a single 2.0/3.0 GSPS ADC to sample one of the I or Q inputs. The output formatting can be programmed to be offset binary or two's complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V to allow for power reduction for well-controlled back planes. 2.0 Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Excellent accuracy and dynamic performance Low power consumption, further reduced at lower Fs Internally terminated, buffered, differential analog inputs R/W SPI Interface for Extended Control Mode Dual-Edge Sampling Mode, in which the I- and Q-channels sample one input at twice the sampling clock rate Test patterns at output for system debug Programmable 15-bit gain and 12-bit plus sign offset Programmable tAD adjust feature 1:1 non-demuxed or 1:2 demuxed LVDS outputs AutoSync feature for multi-chip systems Single 1.9V ± 0.1V power supply 292-ball BGA package (27mm x 27mm x 2.4mm with 1.27mm ball-pitch); no heat sink required LC sampling clock filter for jitter reduction 3.0 Key Specifications (Non-Demux Non-DES Mode, Fs=1.0/1.5 GSPS, Fin = 100 MHz) 10 Bits ■ Resolution ■ Conversion Rate — Dual channels at 1.0/1.5 GSPS (typ) — Single channel at 2.0/3.0 GSPS (typ) 10-18/10-18 (typ) ■ Code Error Rate 9.1/9.0 bits (typ) ■ ENOB 57/56.8 dB (typ) ■ SNR 70/68 dBc (typ) ■ SFDR 2.8/3.1 GHz (typ) ■ Full Power Bandwidth ±0.25/±0.25 LSB (typ) ■ DNL ■ Power Consumption 1.61/1.92W (typ) — Single Channel Enabled 2.77/3.59W (typ) — Dual Channels Enabled 6/6 mW (typ) — Power Down Mode 4.0 Applications ■ Wideband Communications ■ Data Acquisition Systems ■ Digital Oscilloscopes 5.0 Ordering Information Industrial Temperature Range (-40°C < TA < +85°C) ADC10D1000/1500CIUT/NOPB ADC10D1000/1500CIUT ADC10D1000/1500RB NS Package Lead-free 292-Ball BGA Thermally Enhanced Package Leaded 292-Ball BGA Thermally Enhanced Package Reference Board If Military/Aerospace specified devices are required, please contract the National Semiconductor Sales Office/Distributors for availability and specifications. IBIS models are available at: http://www.national.com/analog/adc/ ibis_models. © 2009 National Semiconductor Corporation 300663 www.national.com ADC10D1000/1500 6.0 Block Diagram 30066353 www.DataSheet4U.com FIGURE 1. Simplified Block Diagram www.national.com 2 ADC10D1000/1500 Table of Contents 1.0 General Description ......................................................................................................................... 1 2.0 Features ........................................................................................................................................ 1 3.0 Key Specifications ........................................................................................................................... 1 4.0 Applications .................


DS1873 ADC10D1500 ADC10D1000


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