AD9122 Converter Datasheet

AD9122 Datasheet PDF, Equivalent


Part Number

AD9122

Description

Digital-to-Analog Converter

Manufacture

Analog Devices

Total Page 30 Pages
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Download AD9122 Datasheet PDF


AD9122
Dual, 16-Bit, 1230 MSPS,
TxDAC+ Digital-to-Analog Converter
AD9122
FEATURES
Flexible LVDS interface allows word, byte, or nibble load
Single-carrier W-CDMA ACLR = 82 dBc at 122.88 MHz IF
Analog output: adjustable 8.7 mA to 31.7 mA,
RL = 25 Ω to 50 Ω
Integrated 2×/4×/8× interpolator/complex modulator allows
carrier placement anywhere in the DAC bandwidth
Gain, dc offset, and phase adjustment for sideband
suppression
Multiple chip synchronization interfaces
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
Low power: 1.5 W at 1.2 GSPS, 800 mW at 500 MSPS,
full operating conditions
72-lead, exposed paddle LFCSP
APPLICATIONS
Wireless infrastructure
W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE
Digital high or low IF synthesis
Transmit diversity
Wideband communications: LMDS/MMDS, point-to-point
GENERAL DESCRIPTION
The AD9122 is a dual, 16-bit, high dynamic range digital-to-
analog converter (DAC) that provides a sample rate of 1230 MSPS,
permitting multicarrier generation up to the Nyquist frequency.
The AD9122 TxDAC+® includes features optimized for direct
conversion transmit applications, including complex digital mod-
ulation, and gain and offset compensation. The DAC outputs
are optimized to interface seamlessly with analog quadrature
modulators, such as the ADL537x F-MOD series from Analog
Devices, Inc. A 4-wire serial port interface provides for program-
ming/readback of many internal parameters. Full-scale output
current can be programmed over a range of 8.7 mA to 31.7 mA.
The AD9122 comes in a 72-lead LFCSP.
PRODUCT HIGHLIGHTS
1. Ultralow noise and intermodulation distortion (IMD)
enable high quality synthesis of wideband signals from
baseband to high intermediate frequencies (IF).
2. Proprietary DAC output switching technique enhances
dynamic performance.
3. Current outputs are easily configured for various single-
ended or differential circuit topologies.
4. Flexible LVDS digital interface allows the standard 32-wire
bus to be reduced to one-half or one-quarter of the width.
COMPANION PRODUCTS
IQ Modulators: ADL5370, ADL537x family
IQ Modulators with PLL and VCO: ADRF6701, ADRF670x family
Clock Drivers: AD9516, AD951x family
Voltage Regulator Design Tool: ADIsimPower
Additional companion products on the AD9122 product page
COMPLEX BASEBAND
TYPICAL SIGNAL CHAIN
COMPLEX IF
RF
DC fIF
DIGITAL
BASEBAND
PROCESSOR
2
SIN
COS
2
2/4 I DAC
2/4 Q DAC
NOTES
1. AQM = ANALOG QUADRATURE MODULATOR.
Figure 1.
LO – fIF
ANTIALIASING
FILTER
AQM PA
LO
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009–2011 Analog Devices, Inc. All rights reserved.

AD9122
AD9122
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Product Highlights ........................................................................... 1 
Companion Products ....................................................................... 1 
Typical Signal Chain......................................................................... 1 
Revision History ............................................................................... 3 
Functional Block Diagram .............................................................. 4 
Specifications..................................................................................... 5 
DC Specifications ......................................................................... 5 
Digital Specifications ................................................................... 6 
Digital Input Data Timing Specifications ................................. 6 
AC Specifications.......................................................................... 7 
Absolute Maximum Ratings............................................................ 8 
Thermal Resistance ...................................................................... 8 
ESD Caution.................................................................................. 8 
Pin Configuration and Function Descriptions............................. 9 
Typical Performance Characteristics ........................................... 11 
Terminology .................................................................................... 17 
Differences Between AD9122R1 and AD9122R2 ...................... 18 
Device Marking of AD9122R1 and AD9122R2 ..................... 18 
Theory of Operation ...................................................................... 19 
Serial Port Operation ................................................................. 19 
Data Format ................................................................................ 19 
Serial Port Pin Descriptions...................................................... 19 
Serial Port Options ..................................................................... 20 
Device Configuration Register Map and Descriptions ......... 21 
LVDS Input Data Ports .................................................................. 32 
Word Interface Mode ................................................................. 32 
Byte Interface Mode ................................................................... 32 
Nibble Interface Mode ............................................................... 32 
Interface Timing ......................................................................... 32 
FIFO Operation .......................................................................... 33 
Digital Datapath.............................................................................. 36 
Premodulation ............................................................................ 36 
Interpolation Filters ................................................................... 36 
NCO Modulation ....................................................................... 39 
Datapath Configuration ............................................................ 39 
Determining Interpolation Filter Modes ................................ 40 
Datapath Configuration Examples........................................... 41 
Data Rates vs. Interpolation Modes......................................... 42 
Coarse Modulation Mixing Sequences.................................... 42 
Quadrature Phase Correction................................................... 43 
DC Offset Correction ................................................................ 43 
Inverse Sinc Filter ....................................................................... 43 
DAC Input Clock Configurations ................................................ 44 
Driving the DACCLK and REFCLK Inputs ........................... 44 
Direct Clocking .......................................................................... 44 
Clock Multiplication .................................................................. 44 
PLL Settings ................................................................................ 45 
Configuring the VCO Tuning Band ........................................ 45 
Analog Outputs............................................................................... 46 
Transmit DAC Operation.......................................................... 46 
Auxiliary DAC Operation ......................................................... 47 
Interfacing to Modulators ......................................................... 48 
Baseband Filter Implementation .............................................. 48 
Driving the ADL5375-15 .......................................................... 48 
Reducing LO Leakage and Unwanted Sidebands .................. 49 
Device Power Management........................................................... 50 
Power Dissipation....................................................................... 50 
Temperature Sensor ................................................................... 51 
Multichip Synchronization............................................................ 52 
Synchronization with Clock Multiplication ............................... 52 
Synchronization with Direct Clocking.................................... 53 
Data Rate Mode Synchronization ............................................ 53 
FIFO Rate Mode Synchronization ........................................... 54 
Additional Synchronization Features ...................................... 55 
Interrupt Request Operation ........................................................ 56 
Interrupt Service Routine.......................................................... 56 
Interface Timing Validation.......................................................... 57 
SED Operation............................................................................ 57 
SED Example .............................................................................. 58 
Example Start-Up Routine ............................................................ 59 
Device Configuration ................................................................ 59 
Derived PLL Settings ................................................................. 59 
Derived NCO Settings ............................................................... 59 
Start-Up Sequence...................................................................... 59 
Outline Dimensions ....................................................................... 60 
Ordering Guide .......................................................................... 60 
Rev. B | Page 2 of 60


Features Dual, 16-Bit, 1230 MSPS, TxDAC+ Digital- to-Analog Converter AD9122 FEATURES Fl exible LVDS interface allows word, byte , or nibble load Single-carrier W-CDMA ACLR = 82 dBc at 122.88 MHz IF Analog o utput: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Integrated 2×/4×/8 interpolator/complex modulator allows carrier placement anywhere in the DAC bandwidth Gain, dc offset, and phase ad justment for sideband suppression Multi ple chip synchronization interfaces Hig h performance, low noise PLL clock mult iplier Digital inverse sinc filter Low power: 1.5 W at 1.2 GSPS, 800 mW at 500 MSPS, full operating conditions 72-lea d, exposed paddle LFCSP APPLICATIONS Wi reless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE Digital high or low IF synthesis Transmit diversity Wideband communications: LMDS/MMDS, po int-to-point GENERAL DESCRIPTION The AD 9122 is a dual, 16-bit, high dynamic ra nge digital-toanalog converter (DAC) th at provides a sample rate of 1230 MSPS, permitting multicarrier gene.
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