36VF1601C-70-4C-EK SST36VF1601C Datasheet

36VF1601C-70-4C-EK Datasheet PDF, Equivalent


Part Number

36VF1601C-70-4C-EK

Description

SST36VF1601C

Manufacture

Silicon Storage Technology

Total Page 30 Pages
PDF Download
Download 36VF1601C-70-4C-EK Datasheet PDF


36VF1601C-70-4C-EK
16 Mbit (x8/x16) Dual-Bank Flash Memory
SST36VF1601C / SST36VF1602C
FEATURES:
SST36VF1601C / 1602C16Mb (x8/x16) Dual-Bank Flash Memory
Data Sheet
• Organized as 1M x16 or 2M x8
• Dual Bank Architecture
– 16 Mbit Bottom Sector Protection
- SST36VF1601C: 12 Mbit + 4 Mbit
– 16 Mbit Top Sector Protection
- SST36VF1602C: 4 Mbit + 12 Mbit
• Single 2.7-3.6V for Read and Write Operations
• Superior Reliability
– Endurance: 100,000 cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 6 mA typical
– Standby Current: 4 µA typical
– Auto Low Power Mode: 4 µA typical
• Hardware Sector Protection/WP# Input Pin
– Protects the 4 outermost sectors (8 KWord)
in the larger bank by driving WP# low and
unprotects by driving WP# high
• Hardware Reset Pin (RST#)
– Resets the internal state machine to reading
array data
• Byte# Pin
– Selects 8-bit or 16-bit mode
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Chip-Erase Capability
• Block-Erase Capability
– Uniform 32 KWord blocks
www.DataSheet4U.com
• Erase-Suspend / Erase-Resume Capabilities
• Security ID Feature
– SST: 128 bits
– User: 128 bits
• Fast Read Access Time
– 70 ns
• Latched Address and Data
• Fast Erase and Program (typical):
– Sector-Erase Time: 18 ms
– Block-Erase Time: 18 ms
– Chip-Erase Time: 35 ms
– Program Time: 7 µs
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
– Ready/Busy# pin
• CMOS I/O Compatibility
• Conforms to Common Flash Memory Interface (CFI)
• JEDEC Standards
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-ball TFBGA (6mm x 8mm)
– 48-lead TSOP (12mm x 20mm)
– Non-Pb (lead-free) packages available
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST36VF1601C and SST36VF1602C are 1M x16 or
2M x8 CMOS Read/Write Flash Memory manufactured
with SST’s proprietary, high performance CMOS Super-
Flash technology. The split-gate cell design and thick oxide
tunneling injector attain better reliability and manufacturabil-
ity compared with alternate approaches. The devices write
(Program or Erase) with a 2.7-3.6V power supply and con-
form to JEDEC standard pinouts for x8/x16 memories.
Featuring high performance Program, these devices pro-
vide a typical Program time of 7 µsec and use the Toggle
Bit, Data# Polling, or RY/BY# to detect the completion of
the Program or Erase operation. To protect against inad-
vertent write, the devices have on-chip hardware and Soft-
ware Data Protection schemes. Designed, manufactured,
and tested for a wide spectrum of applications, these
devices are offered with a guaranteed endurance of 10,000
cycles. Data retention is rated at greater than 100 years.
These devices are suited for applications that require con-
venient and economical updating of program, configura-
tion, or data memory. For all system applications, the
devices significantly improve performance and reliability,
while lowering power consumption. Since for any given
voltage range, the SuperFlash technology uses less cur-
rent to program and has a shorter erase time, the total
energy consumed during any Erase or Program operation
is less than alternative flash technologies. These devices
also improve flexibility while lowering the cost for program,
data, and configuration storage applications.
©2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.

36VF1601C-70-4C-EK
Data Sheet
SuperFlash technology provides fixed Erase and Program
times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
To meet high-density, surface-mount requirements, these
devices are offered in 48-ball TFBGA and 48-lead TSOP
packages. See Figures 5 and 6 for pin assignments.
Device Operation
Memory operation functions are initiated using standard
microprocessor write sequences. A command is written by
asserting WE# low while keeping CE# low. The address
bus is latched on the falling edge of WE# or CE#, which-
ever occurs last. The data bus is latched on the rising edge
of WE# or CE#, whichever occurs first.
Auto Low Power Mode
These devices also have the Auto Lower Power mode
which puts them in a near standby mode within 500 ns
after data has been accessed with a valid Read operation.
This reduces the IDD active Read current to 4 µA typically.
While CE# is low, the devices exit Auto Low Power mode
with any address transition or control signal transition used
to initiate another Read cycle, with no access time penalty.
Read Operation
www.DaTthaSehReeet4aUd.coopmeration is controlled by CE# and OE#; both
have to be low for the system to obtain data from the out-
puts. CE# is used for device selection. When CE# is high,
the chip is deselected and only standby power is con-
sumed. OE# is the output control and is used to gate data
from the output pins. The data bus is in a high impedance
state when either CE# or OE# is high. Refer to the Read
cycle timing diagram for further details (Figure 7).
16 Mbit Dual-Bank Flash Memory
SST36VF1601C / SST36VF1602C
Program Operation
These devices are programmed on a word-by-word or
byte-by-byte basis depending on the state of the BYTE#
pin. Before programming, one must ensure that the sector
which is being programmed is fully erased.
The Program operation is accomplished in three steps:
1. Software Data Protection is initiated using the
three-byte load sequence.
2. Address and data are loaded.
During the Program operation, the addresses are
latched on the falling edge of either CE# or WE#,
whichever occurs last. The data is latched on the
rising edge of either CE# or WE#, whichever
occurs first.
3. The internal Program operation is initiated after
the rising edge of the fourth WE# or CE#, which-
ever occurs first. The Program operation, once ini-
tiated, will be completed typically within 7 µs.
See Figures 8 and 9 for WE# and CE# controlled Program
operation timing diagrams and Figure 23 for flowcharts.
During the Program operation, the only valid reads are
Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any
commands issued during an internal Program operation
are ignored.
Sector- (Block-) Erase Operation
These devices offer both Sector-Erase and Block-Erase
operations. These operations allow the system to erase the
devices on a sector-by-sector (or block-by-block) basis. The
sector architecture is based on a uniform sector size of 2
KWord. The Block-Erase mode is based on a uniform block
size of 32 KWord. The Sector-Erase operation is initiated by
executing a six-byte command sequence with a Sector-
Erase command (30H) and sector address (SA) in the last
bus cycle. The Block-Erase operation is initiated by execut-
ing a six-byte command sequence with Block-Erase com-
mand (50H) and block address (BA) in the last bus cycle.
The sector or block address is latched on the falling edge of
the sixth WE# pulse, while the command (30H or 50H) is
latched on the rising edge of the sixth WE# pulse. The inter-
nal Erase operation begins after the sixth WE# pulse. Any
commands issued during the Sector- or Block-Erase opera-
tion are ignored except Erase-Suspend and Erase-
Resume. See Figures 13 and 14 for timing waveforms.
©2006 Silicon Storage Technology, Inc.
2
S71249-06-000
1/06


Features 16 Mbit (x8/x16) Dual-Bank Flash Memory SST36VF1601C / SST36VF1602C SST36VF1601 C / 1602C16Mb (x8/x16) Dual-Bank Flash Memory Data Sheet FEATURES: • Organ ized as 1M x16 or 2M x8 • Dual Bank A rchitecture – 16 Mbit Bottom Sector P rotection - SST36VF1601C: 12 Mbit + 4 M bit – 16 Mbit Top Sector Protection - SST36VF1602C: 4 Mbit + 12 Mbit • Sin gle 2.7-3.6V for Read and Write Operati ons • Superior Reliability – Endura nce: 100,000 cycles (typical) – Great er than 100 years Data Retention • Lo w Power Consumption: – Active Current : 6 mA typical – Standby Current: 4 A typical – Auto Low Power Mode: 4 A typical • Hardware Sector Protecti on/WP# Input Pin – Protects the 4 out ermost sectors (8 KWord) in the larger bank by driving WP# low and unprotects by driving WP# high • Hardware Reset Pin (RST#) – Resets the internal stat e machine to reading array data • Byt e# Pin – Selects 8-bit or 16-bit mode • Sector-Erase Capability – Uniform 2 KWord sectors • Chip-Erase Capability • Block-Erase Capability.
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