CS29

ADVANCE TECHNICAL INFORMATION CS 29 = 800 - 1200 V = 35 A = 23 A Phase Control Thyristor ISOPLUS220TM Electrically Isolated Back Surface VRSM VDSM V 800 1200 VRRM VDRM V 800 1200 CS 29-08io1C CS 29-12io1C Type A C VRRM IT(RMS) IT(AV)M ISOPLUS220TM 1 2 G 3 Isolated back surface * * Patent pending Symbol IT(RMS) IT(AV)M ITSM Test Conditions TVJ = TVJM TC = 95°C; 180° sine (IT(RMS) current limit) TVJ = 45°C; VR = 0 V TVJ = TVJM VR = 0 V t = 10 ms (50 Hz), sine t = 8.3 ms (60 Hz), sine t = 10 ms (50 Hz), sine t = 8.3 ms (60 Hz), sine t = 10 ms (50 Hz), sine t = 8.3 ms (60 Hz), sine t = 10 ms (50 Hz), sine t = 8.3 ms (60 Hz), sine Maximum Ratings 35 23 200 215 175 185 200 195 155 145 150 A A A A A A A2s A2s A2s A2s A/µs l l Features Features l I2t TVJ = 45°C VR = 0 V TVJ = TVJM VR = 0 V l l l (di/dt)cr www.DataSheet4U.com TVJ = TVJM repetitive, IT = 40 A f = 50 Hz, tP =200 µs VD = 2/3 VDRM IG = 0.2 A non repetitive, IT = IT(AV)M diG/dt = 0.2 A/µs TVJ = TVJM; VDR = 2/3 VDRM RGK = ∞; method 1 (linear voltage rise) TVJ = TVJM IT = IT(AV)M tP = 30 µs tP = 300 µs 500 1000 5 2.5 0.5 10 -40...+150 150 -40...+150 A/µs V/µs W W W V °C °C °C V~ °C N / lb g Silicon chip on Direct-Copper-Bond substrate - High power dissipation - Isolated mounting surface - 2500V electrical isolation Low cathode-to-tab capacitance (15pF typical) Planar passivated chips Epoxy meets UL 94V-0 High performance glass passivated chip Long-term stability of leakage current and blocking voltage (dv/...