Document
SPEAR-09-H042
SPEAr™ Head200 ARM 926, 200 K customizable eASIC™ gates, large IP portfolio SoC
Data Brief
Features
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ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD TCM, ETM9 and JTAG interfaces 200K customizable equivalent ASIC gates (16K LUT equivalent) with 8 channels internal DMA high speed accelerator function and 87 dedicated general purpose I/Os Multilayer AMBA 2.0 compliant bus with fMAX 133 MHz Programmable internal clock generator with enhanced PLL function, specially optimized for E.M.I. reduction 16 KB single port SRAM embedded Dynamic RAM interface: 8/16 bit DDR, 8/16 bit SDRAM SPI interface connecting serial ROM and Flash devices 2 USB 2.0 Host independent ports with integrated PHYs USB 2.0 device with integrated PHY MAC 10/100 with MII management
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LFBGA289
Real time clock WatchDog 4 general purpose timers Operating temperature: - 40 to 85 °C Package: LFBGA289 (15x15x1.7mm pitch 0.8mm)
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Description
SPEAr Head200 is a powerful digital engine belonging to SPEAr family, the innovative customizable system-on-chip. The device integrates an ARM core with a large set of proven IPs (Intellectual Properties) and a configurable logic block that allows very fast customization of unique and/or proprietary solutions, with low effort and low investment. Optimized for embedded applications.
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1 independent UART up to 115 Kbps (software flow control mode) I2C master mode, fast and slow speed 6 general purpose I/Os Device summary
Order code SPEAR-09-H042
Table 1.
Package LFBGA289 (15x15x1.7mm)
Packing Tray
January 2008
Rev 1
1/16
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For further information contact your local STMicroelectronics sales office.
Contents
SPEAR-09-H042
Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 2.3 2.4 2.5 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 eASIC GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 External FPGA emulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Dynamic RAM data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 3.2 3.3 Interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Ballout top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 5
Package outline assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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SPEAR-09-H042
Introduction
1
Introduction
This data brief describes the differences between SPEAr Head200 (SPEAR-09-H022) and the one packaged in LFBGA289 balls 0.8mm pitch (SPEAR-09-H042). In this document the main package characteristics are described as well as the chip features modifications. The reference specifications, for the SPEAR-09-H022 are available on the web at: www.st.com.
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Features modification
SPEAR-09-H042
2
Features modification
To fit the new small package a number of features has been reduced or limited:
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Analog to digital converter (ADC) eASIC GPIOs External FPGA emulation mode Dynamic RAM data path UARTs
2.1
Analog to digital converter (ADC)
ADC feature has been completely deleted so the 16 analog channels, the related test output, the power balls and the reference voltages have been removed.
2.2
eASIC GPIOs
SPEAR-09-H022 features 112 GPIOs in the eASIC customizable part, some of these I/Os have been removed, but 87 are still available on SPEAR-09-H042. Unusable hidden eASIC GPIOs (74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 96, 98, 100-111) must be configured as inputs.
2.3
External FPGA emulation mode
SPEAR-09-H022 has the capability to emulate the internal eASIC behavior with an external FPGA through the component GPIOs. This feature has been completely removed on SPEAR-09-H042 hence the developement boards must use the 420 PBGA components.
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2.4
Dynamic RAM data path
The SPEAr component features a multi purpose memory controller to interface SDRAM or DDR memories able to work with different data path widths. While SPEAR-09-H022 handles 8 and 16-bit DDRs or 8, 16 and 32-bit SDRAMs, on SPEAR-09-H042 to save 16 data balls and the related "data mask" balls, the SDR.