LY622568

 Rev. 2.8 LY622568 256K X 8 BIT LOW POWER CMOS SRAM REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 2.0 Rev. 2.1 Rev. 2.2 Rev. 2.3 Rev. 2.4 Rev. 2.5 Rev. 2.6 Rev. 2.7 Rev. 2.8 Description Initial Issue Revised ISB1/IDR/Test Condition of ICC Adding PKG type : 32 P-DIP Revised Test Condition of ISB1/IDR Adding SL Spec. Revised ABSOLUTE MAXIMUN RATINGS Added ISB1/IDR values when TA = 25℃ and TA = 40℃ Revised ISB1 (MAX) of SL grade Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Added packing type in ORDERING INFORMATION Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Revised -35ns to -45ns Spec. Revised VDR Revised PACKAGE OUTLINE DIMENSION in page 8/9/11 Revised ORDERING INFORMATION in page 12 Revised VIL(max) from 0.6V to 0.8V Correct ORDERING INFORMATION Typo. Deleted WRITE CYCLE Notes : 1. WE#, CE# must be high or CE2 must be low during all address transitions in page 6. Revised ORDERING INFORMATION in page 14 Removed Package Type : PDIP Issue Date Aug.29.2005 Oct.31.2005 May.14.2007 Jul.26.2007 Mar.30.2009 Sep.11.2009 May.7.2010 Aug.30.2010 May 8.2014 May.20.2016 Jun.28.2016 Apr.08. 2019 Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0  Rev. 2.8 LY622568 256K X 8 BIT LOW POWER CMOS SRAM FEATURES  Fast access time : 45/55/70ns  Low power ...