Document
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
Rev. 7 — 26 September 2014
Product data sheet
1. General description
The PCA9701/PCA9702 are low power 18 V tolerant SPI General Purpose Input (GPI) shift register designed to monitor the status of switch inputs. It generates an interrupt when one or more of the switch inputs change state. The input level is recognized as a HIGH when it is greater than 0.7 VDD and as a LOW when it is less than 0.4 VDD (minimum threshold of 2 V at 5 V node). The PCA9701 can monitor up to 16 switch inputs and the PCA9702 can monitor up to 8 switch inputs.
The falling edge of the CS pin samples the input port status and clears the interrupt. When CS is LOW, the rising edge of the SCLK loads the shift register and shifts the value out of the shift register. The serial input is sampled on the falling edge of SCLK.
Each of the input ports has a 18 V breakdown ESD protection circuit. When used with a series resistor (minimum 100 k), the input can connect to a 12 V battery and support double battery, reverse battery, 27 V jump start and 40 V load dump conditions in automotive applications. Higher voltages can be tolerated on the inputs depending on the series resistor used to limit the input current.
With both the high breakdown voltage and high ESD, these devices are useful for both automotive and mobile applications.
The PCA9703/PCA9704 are new pin compatible devices for the PCA9701/PCA9702 which have an interrupt masking feature allowing selected inputs to not generate interrupts and provides higher ground offset of 0.55 VDD (minimum of 2.5 V at 5 V node) with minimum hysteresis of 0.05 VDD (minimum of 225 mV at 5 V node).
2. Features and benefits
16 general purpose input ports (PCA9701) or 8 general purpose input ports (PCA9702)
18 V tolerant input ports with 100 k external series resistor Input LOW threshold 0.4 VDD with minimum of 2 V at VDD = 4.5 V Open-drain interrupt output Interrupt enable pin (INT_EN) disables interrupt output VDD range: 2.5 V to 5.5 V IDD is very low 2.5 A maximum SPI serial interface with speeds up to 5 MHz ESD protection exceeds 8 kV HBM per JESD22-A114, 350 V MM, and 1000 V CDM
per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Operating temperature range: 40 C to +125 C
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
PCA9701 offered in SO24, TSSOP24 and HWQFN24 packages PCA9702 offered in TSSOP16 package
3. Applications
Body control modules Switch monitoring Industrial equipment Cellular telephones Emergency lighting SBC wake pin extension
4. Ordering information
Table 1. Ordering information
Type number
Topside marking
Package
Name
Description
Version
PCA9701D
PCA9701D SO24
plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
PCA9701HF
9701
HWQFN24 plastic thermal enhanced very very thin quad flat package; SOT994-1 no leads; 24 terminals; body 4 4 0.75 mm
PCA9701PW
PCA9701PW TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
PCA9702PW
PCA9702
TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
4.1 Ordering options
Table 2. Ordering options
Type number
Orderable part Package Packing method number
PCA9701D
PCA9701D,118 SO24
Reel 13” Q1/T1 *standard mark SMD
PCA9701HF
PCA9701HF,118 HWQFN24 Reel 13” Q1/T1 *standard mark SMD
PCA9701PW
PCA9701PW,118 TSSOP24 Reel 13” Q1/T1 *standard mark SMD
PCA9702PW
PCA9702PW,118 TSSOP16 Reel 13” Q1/T1 *standard mark SMD
Minimum
Temperature range
order quantity
1000
Tamb = 40 C to +125 C
6000
Tamb = 40 C to +125 C
2500
Tamb = 40 C to +125 C
2500
Tamb = 40 C to +125 C
PCA9701_PCA9702
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 26 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
2 of 29
NXP Semiconductors
5. Block diagram
PCA9701/PCA9702
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
VDD INT
IN0
DFF0
IN1
DFF1
INn(1)
DFFn(1)
INPUT STATUS REGISTER
SHIFT REGISTER
VSS
(1) n = 15 for PCA9701; n = 7 for PCA9702
Fig 1. Block diagram of PCA9701; PCA9702
INT_EN
20 μA
SDOUT SDIN SCLK CS
002aac422
PCA9701_PCA9702
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 26 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
3 of 29
NXP Semiconductors
6. Pinning information
6.1 Pinning
SDOUT 1 INT 2
INT_EN 3 IN0 4 IN1 5 IN2 6 IN3 7 IN4 8 IN5 9 IN6 10 IN7 11 VSS 12
PCA9701D
24 VDD 23 SDIN 22 SCLK 21 CS 20 IN15 19 IN14 18 IN13 17 IN12 16 IN11 15 IN10 14 IN9 13 IN8
002aac636
Fig 2. Pin configuration for SO24
24 INT_EN 23 INT 22 SDOUT 21 VDD 20 SDIN 19 SCLK
terminal 1 index.