Document
NBXSBB023, NBXSBA023 3.3 V, 400 MHz LVPECL Clock Oscillator
The NBXSBB023/NBXSBA023 single frequency crystal oscillator (XO) is designed to meet today’s requirements for 3.3 V LVPECL clock generation applications. The device uses a high Q fundamental crystal and Phase Lock Loop (PLL) multiplier to provide 400 MHz, ultra low jitter and phase noise LVPECL differential output. This device is a member of ON Semiconductor’s PureEdget clock family that provides accurate and precision clock solutions. Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape and reel in quantities of 1,000. Frequency stability option available as either 50 PPM NBXSBA023 or 20 PPM NBXSBB023.
Features http://onsemi.com
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6 PIN CLCC TBD SUFFIX CASE 848AB
LVPECL Differential Output Uses High Q Fundamental Mode Crystal and PLL Multiplier Ultra Low Jitter and Phase Noise − 0.5 ps (12 kHz − 20 MHz) Hermetically Sealed Ceramic SMD Package RoHS Compliant Operating Range 3.3 V ±10% Total Frequency Stability − $20 PPM or $50 PPM
MARKING DIAGRAMS
NBXSBB023 400 AWLYYWW NBXSBA023 400 AWLYYWW
Applications
• Networking • SPI−4
NBXSBB023 = NBXSBB023 (±20 PPM)* NBXSBA023 = NBXSBA023 (±50 PPM) 400 = Output Frequency (MHz) A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week
ORDERING INFORMATION
VDD 6 www.DataSheet4U.com PLL Clock Multiplier CLK CLK 5 4 Device NBXSBB023LN1TAG* NBXSBA023LN1TAG Crystal NBXSBA023LNHTAG Package CLCC−6 (Pb−Free) CLCC−6 (Pb−Free) CLCC−6 (Pb−Free) Shipping† 1000/ Tape & Reel 1000/ Tape & Reel 100/ Tape & Reel
1 OE
2 NC
3 GND
Figure 1. Simplified Logic Diagram
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. * Please contact factory for availability
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2009
March, 2009 − Rev. 1
1
Publication Order Number: NBXSBB023/D
NBXSBB023, NBXSBA023
OE NC GND 1 2 3 6 5 4 VDD CLK CLK
Figure 2. Pin Connections (Top View) Table 1. PIN DESCRIPTION
ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Pin No. 1 2 3 4 5 6 Symbol OE NC I/O Description LVTTL/LVCMOS Control Input − Output Enable Pin. When left floating pin defaults to logic HIGH and output is active. See OE pin description Table 2. No Connect. Ground 0 V. GND CLK CLK VDD Power Supply LVPECL Output LVPECL Output Power Supply Non−Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to VTT = VDD − 2 V. Inverted Clock Output. Typically loa.