IS43R32400A

IS43R32400A 4Meg x 32 128-MBIT DDR SDRAM FEATURES ISSI DEVICE OVERVIEW ® PRELIMINARY INFORMATION FEBRUARY 2006 Clock Frequency: 200, 166, 100 MHz Power supply (VDD and VDDQ): 2.5V SSTL 2 interface Four internal banks to hide row Pre-charge and Active operations Commands and addresses register on positive clock edges (CLK) Bi-directional Data Strobe signal for data capture Differential clock inputs (CLK and CLK) for two data accesses per clock cycle Data Mask feature for Writes supported DLL aligns data I/O and Data Strobe transitions with clock inputs Half-strength and Matched drive strength options Programmable burst length for Read and Write operations Programmable CAS Latency (3, 4, 5 clocks) ISSI’s 128-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 134,217,728-bit memory array is internally organized as four banks of 32M-bit to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence and CAS latency enable further advantages. The device is available in 32-bit data word size. Input data is registered on the I/O pins on both edges of Data Strobe signal(s), while output data is referenced to both edges of Data Strobe and both edges of CLK. Commands are registered on the positive edges of CLK. Auto Refresh, ...