Document
CY8C28243, CY8C28403, CY8C28413 PRELIMINARY CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 ®
PSoC Programmable System-on-Chip
Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on All GPIO ❐ Analog Input on All GPIO ❐ 30 mA Analog Outputs on GPIO ❐ Configurable Interrupt on all GPIO
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Features
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Varied Resource Options Within One PSoC Device Group Powerful Harvard Architecture Processor ❐ M8C Processor Speeds up to 24 MHz ❐ 8x8 Multiply, 32-Bit Accumulate ❐ Low Power at High Speed ❐ 3.0V to 5.25V Operating Voltage ❐ Operating Voltages Down to 1.0V Using On-Chip Switched Mode Pump (SMP) ❐ Industrial Temperature Range: -40°C to +85°C
Advanced Reconfigurable Peripherals (PSoC Blocks) ❐ Up to 12 Rail-to-Rail Analog PSoC Blocks Provide: • Up to 14-Bit ADCs • Up to 9-Bit DACs • Programmable Gain Amplifiers • Programmable Filters and Comparators • Multiple ADC configurations • Dedicated SAR ADC, up to 118 ksps with Sample and Hold • Up to 4 Synchronized or Independent Delta-Sigma ADCs for Advanced Applications ❐ Up to 4 Limited Type E Analog Blocks Provide: • Dual Channel Capacitive Sensing Capability • Comparators with Programmable DAC Reference • Up to 10-bit Single-Slope ADCs ❐ Up to 12 Digital PSoC Blocks Provide: • 8 to 32-Bit Timers, Counters, and PWMs • Shift Register, CRC, and PRS Modules • Up to 3 Full-Duplex UARTs www.DataSheet4U.com • Up to 6 Half-Duplex UARTs • Multiple Variable Data Length SPI™ Masters or Slaves • Connectable to All GPIO ❐ Complex Peripherals by Combining Blocks
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Additional System Resources 2 ❐ Up to 2 Hardware I C Resources • Each Resource Implements Slave, Master, or Multi-Master Modes • Operation Between 0 and 400 kHz ❐ Watchdog and Sleep Timers ❐ User-Configurable Low Voltage Detection ❐ Flexible Internal Voltage References ❐ Integrated Supervisory Circuit ❐ On-Chip Precision Voltage Reference Complete Development Tools ❐ Free Development Software (PSoC Designer™) ❐ Full Featured In-Circuit Emulator, and Programmer ❐ Full Speed Emulation ❐ Flexible and Functional Breakpoint Structure ❐ 128K Trace Memory
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System Block Diagram
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
PSoC CORE
System Bus
Global Digital Interconnect SRAM 1K Interrupt Controller SROM
Analog Drivers
Global Analog Interconnect Flash 16K Sleep and Watchdog
CPU Core (M8C)
Precision, Programmable Clocking ❐ Internal ±2.5% 24/48 MHz Main Oscillator ❐ Optional 32.768 kHz Crystal for Precise On-Chip Clocks ❐ Optional External Oscillator, up to 24 MHz ❐ Internal Low Speed, Low Power Oscillator for Watchdog and Sleep Functionality Flexible On-Chip Memory ❐ 16K Bytes Flash Program Storage 50,000 Erase/Write Cycles ❐ 1K Bytes SRAM Data Storage ❐ In-System Serial Programming (ISSP™) ❐ Partial Flash Updates ❐ Flexible Protection Modes ❐ EEPROM Emulation in Flash Programmable Pin Configurations ❐ 25 mA Sink, 10 mA Drive on All GPIO
Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital Block Array
ANALOG SYSTEM
Analog Block Array
Analog Ref.
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Analog Input Muxing
Digital Clocks
2 MACs
4 Type 2 2 I2C Decimators Blocks
POR and LVD System Resets
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Internal Voltage Ref.
Switch Mode Pump
SYSTEM RESOURCES
Cypress Semiconductor Corporation Document Number: 001-48111 Rev. *C
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198 Champion Court
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San Jose, CA 95134-1709 • 408-943-2600 Revised March 26, 2009
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PRELIMINARY
CY8C28xxx
PSoC Functional Overview
The PSoC family consists of many devices with On-Chip Controllers. These devices are designed to replace multiple traditional MCU based system components with one low cost single chip programmable component. A PSoC device includes configurable analog blocks, digital blocks, and interconnections. This architecture enables the user to create customized peripheral configurations to match the requirements of each individual application. In addition, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts and packages. The CY8C28xxx group of PSoC devices described in this data sheet have multiple resource configuration options available. Therefore, not every resource mentioned in this data sheet is available for each CY8C28xxx subgroup. The CY8C28x45 subgroup has a full feature set of all resources described. There are six more segmented subgroups that allow designers to use a device with only the resources and functionality necessary for a specific application. See Table 2 on page 6 to determine the resources available for each CY8C28xxx subgroup. The same information is also presented in more detail in the Ordering Information section. The architecture for this specific PSoC device family, as shown in the System Block Diagram on page 1, consists of four main areas: PSoC Core, Digital System, Analog System, and System Resources. The configurable global bus system allows all the device resources to be combined into a complete custom system. PSoC C.