UPD72852A

DATA SHEET MOS INTEGRATED CIRCUIT µPD72852A IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI The µPD72852A is a two-port physical layer LSI that complies with the IEEE1394a-2000 specifications. FEATURES The two-port physical layer LSI complies with IEEE1394a-2000 Fully interoperable with IEEE1394 std 1394 Link (FireWireTM, i.LINKTM) Meets IntelTM Mobile Power Guideline 2000 Full IEEE1394a-2000 support includes: Suspend/Resume, connection debounce, arbitrated short bus reset, multi-speed concatenation, arbitration acceleration, fly-by concatenation Suspend Debounce timer for ESD “BIAS Detected” signal output Double speed signal filter for BIAS Ringing Small package: 64-pin plastic LQFP Super low power : 68 mA (Operating mode) : 115 µA (Suspend mode) Data rate: 400/200/100 Mbps Supports PHY pinging and remote PHY access packets 3.3 V single power supply (if power not supplied via node: 3.0 V single power supply) 24.576 MHz crystal clock generation, 393.216 MHz PLL multiplying frequency 64-bit flexible register incorporated in PHY register www.DataSheet4U.com Electrically isolated Link interface Supports LPS/Link-on as part of PHY/Link interface External filter capacitors for PLL not required Extended Resume signaling for compatibility with legacy DV devices System power management by signaling of node power class information Cable power monitor (CPS) is equipped ORDERING INFORMATION Part number Package 64-pin plastic LQFP (10 × 10)...