46V16M16

PRELIMINARY‡ 256Mb: x4, x8, x16 DDR333 SDRAM Addendum DOUBLE DATA RATE (DDR) SDRAM FEATURES 167 MHz Clock, 333 Mb/s/p data rate VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two - one per byte) Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Differential clock inputs (CK and CK#) Commands entered on each positive CK edge DQS edge-aligned with data for READs; centeraligned with data for WRITEs DLL to align DQ and DQS transitions with CK Four internal banks for concurrent operation Data mask (DM) for masking write data (x16 has two - one per byte) Programmable burst lengths: 2, 4, or 8 Concurrent Auto Precharge option supported Auto Refresh and Self Refresh Modes FBGA package available 2.5V I/O (SSTL_2 compatible) tRAS lockout (tRAP = tRCD) Backwards compatible with DDR200 and DDR266 MT46V64M4 – 16 Meg x 4 x 4 banks MT46V32M8 – 8 Meg x 8 x 4 banks MT46V16M16 – 4 Meg x 16 x 4 banks For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/dramds DDR333 COMPATIBILITY DDR333 meets or surpasses all DDR266 timing requirements thus assuring full backwards compatibility with current DDR designs. In addition, these devices support concurrent auto-precharge and tRAS lockout for improved timing performance. The 256Mb, DDR333 device will support an (tREFI) average periodic ref...