CY7C1371B

73B CY7C1371B CY7C1373B 512K x 36/1M x 18 Flow-Thru SRAM with NoBL™ Architecture Features Pin compatible and functionally equivalent to ZBT devices Supports 117-MHz bus operations with zero wait states — Data is transferred on every clock Internally self-timed output buffer control to eliminate the need to use asynchronous OE Registered inputs for flow-thru operation Byte Write capability Common I/O architecture Fast clock-to-output times — 7.5 ns (for 117-MHz device) — 8.5 ns (for 100-MHz device) — 10.0ns (for 83-MHz device) Single 3.3V –5% and +10% power supply VDD Separate VDDQ for 3.3V or 2.5V I/O Clock enable (CEN) pin to suspend operation Synchronous self-timed writes Available in 100 TQFP and 119 BGA packages Burst capability – linear or interleaved burst order JTAG boundary scan for BGA packaging version Automatic power down available using ZZ mode or CE deselect Functional Description The CY7C1371B/CY7C1373B is 3.3V, 512K × 36 and 1M × 18 synchronous flow-thru burst SRAMs, respectively designed to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371B/ CY7C1373B is equipped with the advanced No Bus Latency™ (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write/Read transitions.The CY7C1371B/CY7...