CY2SSTV850

STV850 CY2SSTV850 Differential Clock Buffer/Driver Features Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications 1:10 differential outputs External Feedback pins (FBINT, FBINC) are used to synchronize the outputs to the clock input SSCG: Spread Aware™ for EMI reduction 48-pin SSOP and TSSOP packages Conforms to JEDEC JC40 and JC42.5 DDR specifications Description This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD operation and differential data input and output levels. This device is a zero-delay buffer that distributes a differential clock input pair (CLKINT, CLKINC) to ten differential pair of clock outputs (YT[0:9], YC[0:9]) and one differential pair feedback clock output (FBOUTT, FBOUTC). The clock outputs are individually controlled by the serial inputs SCLK and SDATA. The two-line serial bus can set each output clock pair (YT[0:9], YC[0:9]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. The PLL in this device uses the input clocks (CLKINT,CLKINC) and the feedback clocks (FBINT,FBINC) to provide high-performance, low-skew, low-jitter output differential clocks. Block Diagram Pin Configuration 10 YT0 YC0 YT1 YC1 YT2 YC2 SCLK SDATA Serial Interface Logic YT4 YC4 YT5 YC5 YT6 YC6 www.DataSheet4U.com CLKINT CLKINC PLL FBINT FBINC YT7 YC7 YT8 YC8 YT9 YC9 CY2SSTV850 YT3 YC3 AVDD FBOUTT FBOUTC VSS YC0 YT0 VDDQ YT1 YC1 VSS VSS YC2 YT2 VDD SCLK CLKINT CLKINC VDD...