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ISPCLOCK5510 Dataheets PDF



Part Number ISPCLOCK5510
Manufacturers Lattice Semiconductor
Logo Lattice Semiconductor
Description In-System Programmable Zero-Delay
Datasheet ISPCLOCK5510 DatasheetISPCLOCK5510 Datasheet (PDF)

ispClock 5300S Family ™ In-System Programmable, Zero-Delay Universal Fan-Out Buffer, Single-Ended October 2007 Preliminary Data Sheet DS1010 Features ■ Four Operating Configurations • • • • Zero delay buffer Zero delay and non-zero delay buffer Dual non-zero delay buffer Non-zero delay buffer with output divider • Up to +/- 5ns skew range • Coarse and fine adjustment modes ■ Up to Three Clock Frequency Domains ■ Flexible Clock Reference and External Feedback Inputs • Programmable single-ended .

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ispClock 5300S Family ™ In-System Programmable, Zero-Delay Universal Fan-Out Buffer, Single-Ended October 2007 Preliminary Data Sheet DS1010 Features ■ Four Operating Configurations • • • • Zero delay buffer Zero delay and non-zero delay buffer Dual non-zero delay buffer Non-zero delay buffer with output divider • Up to +/- 5ns skew range • Coarse and fine adjustment modes ■ Up to Three Clock Frequency Domains ■ Flexible Clock Reference and External Feedback Inputs • Programmable single-ended or differential input reference standards - LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Differential HSTL, Differential SSTL • Clock A/B selection multiplexer • Programmable Feedback Standards - LVTTL, LVCMOS, SSTL, HSTL • Programmable termination ■ 8MHz to 267MHz Input/Output Operation ■ Low Output to Output Skew (<100ps) ■ Low Jitter Peak-to-Peak (< 70 ps) ■ Up to 20 Programmable Fan-out Buffers • Programmable single-ended output standards and individual enable controls - LVTTL, LVCMOS, HSTL, eHSTL, SSTL • Programmable output impedance - 40 to 70Ω in 5Ω increments • Programmable slew rate • Up to 10 banks with individual VCCO and GND - 1.5V, 1.8V, 2.5V, 3.3V ■ All Inputs and Outputs are Hot Socket Compliant ■ Full JTAG Boundary Scan Test In-System Programming Support ■ Exceptional Power Supply Noise Immunity ■ Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges ■ 48-pin and 64-pin TQFP Packages ■ Applications • • • • Circuit board common clock distribution PLL-based frequency generation High fan-out clock buffer Zero-delay clock buffer ■ Fully Integrated High-Performance PLL • • • • • Programmable lock detect Three “Power of 2” output dividers (5-bit) Programmable on-chip loop filter Compatible with spread spectrum clocks Internal/external feedback www.DataSheet4U.com (Skew) Per ■ Precision Programmable Phase Adjustment Output • 8 settings; minimum step size 156ps - Locked to VCO frequency ispClock5300S Family Functional Diagram LO CK PLL _ BYPASS REFA / REFP REFB / REFN + OUTPUT DIVIDERS 1 0 1 SKEW CONTROL OUTPUT DRIVERS OUTPUT 1 PHASE FREQ. DETECT LOOP FILTER V0 5-Bit VCO 0 V1 5-bit REFSEL V2 5-bit OUTPUT ROUTING MATRIX FBK OUTPUT N © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 DS1010_01.4 Lattice Semiconductor ispClock5300S Family Data Sheet General Description The ispClock5300S is an in-system-programmable zero delay universal fan-out buffer for use in clock distribution applications. The ispClock5312S, the first member of the ispClock5300S family, provides up to 12 single-ended ultra low skew outputs. Each pair of outputs may be independently configured to support separate I/O standards (LVTTL, LVCMOS -3.3V.


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