AS7C31025A

January 2001 Advance Information ® AS7C1025A AS7C31025A www.DataSheet4U.com 5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) Features AS7C1025A (5V version) AS7C31025A (3.3V version) Industrial and commercial temperatures Organization: 131,072 x 8 bits High speed - 10/10/12/15/20 ns address access time - 3/3/4/5 ns output enable access time Low power consumption: ACTIVE - 660 mW (AS7C1025A) / max @ 10 ns (5V) - 324 mW (AS7C31025A) / max @ 10 ns (3.3V) Low power consumption: STANDBY - 55 mW (AS7C1025A) / max CMOS (5V) - 36 mW (AS7C31025A) / max CMOS (3.3V) Latest 6T 0.25u CMOS technology 2.0V data retention Easy memory expansion with CE, OE inputs Center power and ground TTL/LVTTL-compatible, three-state I/O JEDEC-standard packages - 32-pin, 300 mil SOJ - 32-pin, 400 mil SOJ - 32-pin, TSOP II ESD protection ≥ 2000 volts Latch-up current ≥ 200 mA 32-pin TSOP II A0 A1 A2 A3 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 GND VCC I/O5 I/O4 A12 A11 A10 A9 A8 Pin arrangement Logic block diagram VCC GND Input buffer A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O7 Row decoder 512×256×8 Array (1,048,576) Sense amp 32-pin SOJ (300 mil) 32-pin SOJ (400 mil) I/O0 WE OE CE A0 A1 A2 A3 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 GND VCC ...