KK74AC112

TECHNICAL DATA www.DataSheet4U.com KK74AC112 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The KK74AC112 is identical in pinout to the LS/ALS112, HC/HCT112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs. Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 µA; 0.1 µA @ 25°C High Noise Immunity Characteristic of CMOS Devices Outputs Source/Sink 24 mA ORDERING INFORMATION KK74AC112N Plastic KK74AC112D SOIC TA = -40° to 85° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Set L H L H H H H H H H PIN 16=VCC PIN 8 = GND Reset H L L H H H H H H H L H Clock X X X J X X X L L H H X X X K X X X L H L H X X X Outputs Q H L L * Q L H L* H L No Change L H Toggle No Change No Change No Change * Both outputs will remain low as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously X = Don’t Care 1 www.DataSheet4U.com KK74AC112 MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Pl...