3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Translator
Freescale Semiconductor Technical Data
MC100ES60T22 Rev 2, 2/2005
www.DataSheet4U.com
3.3 V Dual LVTTL/LVCMOS to Diffe...
Description
Freescale Semiconductor Technical Data
MC100ES60T22 Rev 2, 2/2005
www.DataSheet4U.com
3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Translator
The MC100ES60T22 is a low skew dual LVTTL/LVCMOS to differential LVPECL translator. The low voltage PECL levels, small package, and dual gate design are ideal for clock translation applications. Features 280 ps typical propagation delay 100 ps max output-to-output skew LVPECL operating range: VCC = 3.135 V to 3.8 V 8-lead SOIC and 8-lead TSSOP packages Ambient temperature range –40°C to +85°C
MC100ES60T22
D SUFFIX 8-LEAD SOIC PACKAGE CASE 751-06
DT SUFFIX 8-LEAD TSSOP PACKAGE CASE 1640-01
Q0
1
8
VCC
ORDERING INFORMATION
Device MC100ES60T22D Package SOIC-8 SOIC-8 TSSOP-8 TSSOP-8
Q0
2 LVPECL LVTTL/LVCMOS
7
D0
MC100ES60T22DR2 MC100ES60T22DT MC100ES60T22DTR2
Q1
3
6
D1 Pin D0, D1 Qn, Qn
PIN DESCRIPTION
Function LVTTL/LVCMOS Inputs LVPECL Differential Outputs Positive Supply Negative Supply
Q1
4
5
GND
VCC GND
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Table 1. General Specifications
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection θJA Thermal Resistance (Junction-to-Ambient) Human Body Model Machine Model 0 LFPM, 8 SOIC 500 LFPM, 8 SOIC 0 LFPM, 8 TSSOP 500 LFPM, 8 TSSOP
www.DataSheet4U.com Value
75 kΩ 75 kΩ > 2000 V > 200 V 190°C/W 130°C/W 185°C/W 140°C/W
Meets or exceeds JEDEC Spec EIA/...
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