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MC100ES7111 Dataheets PDF



Part Number MC100ES7111
Manufacturers Motorola
Logo Motorola
Description LOW VOLTAGE 1:10 DIFFERENTIAL LVDS CLOCK FANOUT BUFFER
Datasheet MC100ES7111 DatasheetMC100ES7111 Datasheet (PDF)

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order Number: MC100ES7111/D Rev 0, 12/2002 www.DataSheet4U.com Preliminary Information Low Voltage 1:10 Differential LVDS Clock Fanout Buffer The Motorola MC100ES7111 is a LVDS differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES7111 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the d.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order Number: MC100ES7111/D Rev 0, 12/2002 www.DataSheet4U.com Preliminary Information Low Voltage 1:10 Differential LVDS Clock Fanout Buffer The Motorola MC100ES7111 is a LVDS differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES7111 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are high performance clock distribution in computing, networking and telecommunication systems. MC100ES7111 LOW–VOLTAGE 1:10 DIFFERENTIAL LVDS CLOCK FANOUT DRIVER • • • • • • • • • Features: 1:10 differential clock fanout buffer 50 ps maximum device skew1 SiGe technology Supports DC to 1000 MHz operation1 of clock or data signals LVDS compatible differential clock outputs PECL and HSTL/LVDS compatible differential clock inputs 3.3V power supply Supports industrial temperature range Standard 32 lead LQFP package FA SUFFIX 32–LEAD LQFP PACKAGE CASE 873A Functional Description The MC100ES7111 is designed for low skew clock distribution systems and supports clock frequencies up to 1000 MHz1. The device accepts two clock sources. The CLK0 input accepts LVDS or HSTL compatible signals and CLK1 accepts PECL compatible signals. The selected input signal is distributed to 10 identical, differential LVDS compatible outputs. The output enable control is synchronized internally preventing output runt pulse generation. Outputs are only disabled or enabled when the outputs are already in logic low state (true outputs logic low, inverted outputs logic high). The internal synchronizer eliminates the setup and hold time requirements for the external clock enable signal. The device is packaged in a 7x7 mm2 32-lead LQFP package. This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 1. AC specifications are design targets and subject to change © Motorola, Inc. 2002 MC100ES7111 www.DataSheet4U.com Q3 Q3 Q4 Q4 Q5 Q5 Q6 18 Q6 17 16 15 14 13 VCC Q7 Q7 Q8 Q8 Q9 Q9 VCC 12 11 10 9 1 2 3 4 5 6 7 8 GND Q0 Q0 VCC 24 VCC Q2 Q2 Q1 Q1 Q0 Q0 VCC 25 26 27 28 23 22 21 20 19 CLK0 CLK0 0 1 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 OE Q5 Q5 Q6 Q6 Q7 Q7 Q8 Q8 Q9 Q9 MC100ES7111 29 30 31 32 VCC CLK1 CLK1 CLK_SEL CLK_SEL CLK0 CLK0 CLK1 1 Figure 1. MC100ES7111 Logic Diagram Table 1. PIN CONFIGURATION Pin CLK0, CLK0 CLK1, CLK1 CLK_SEL OE Q[0–9], Q[0–9] GND VCC I/O Input Input Input Input Output Supply Supply Type HSTL/LVDS PECL LVCMOS LVCMOS LVDS Figure 2. 32–Lead Package Pinout (Top View) Function Differential HSTL or LVDS reference clock signal input Differential PECL reference clock signal input Reference clock input select Output enable/disable. OE is synchronous to the input reference clock which eliminates possible output runt pulses when the OE state is changed. Differential clock outputs Negative power supply Positive power supply of the device (3.3V) Table 2. FUNCTION TABLE Control CLK_SEL OE Default 0 0 0 CLK0, CLK0 (HSTL/LVDS) is the active differential clock input Q[0-9], Q[0-9] are active. Deassertion of OE can be asynchronous to the reference clock without generation of output runt pulses. CLK1, CLK1 (PECL) is the active differential clock input Q[0-9] = L, Q[0-9] =H (outputs disabled). Assertion of OE can be asynchronous to the reference clock without generation of output runt pulses. MOTOROLA 2 CLK1 VCC OE OE TIMING SOLUTIONS MC100ES7111 www.DataSheet4U.com Table 3. Absolute Maximum Ratingsa Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC + 0.3 VCC + 0.3 ±20 ±50 125 Unit V V V mA mA °C Condition TFunc Functional temperature range TA = -40 TJ = +110 °C a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 4. General Specifications Symbol MM HBM CDM LU CIN θJA Characteristics ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model) Latch-up immunity Input Capacitance Thermal resistance junction to ambient JESD 51-3, single layer test board Min 200 2000 TBD 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 Typ Max Unit V V V mA pF °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 88.


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