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STL35NF10
N-CHANNEL 100V - 0.025Ω - 35A PowerFLAT™ LOW GATE CHARGE STripFET™ MOSFET
PRELIMINARY DAT...
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STL35NF10
N-CHANNEL 100V - 0.025Ω - 35A PowerFLAT™ LOW GATE CHARGE STripFET™ MOSFET
PRELIMINARY DATA TYPE STL35NF10
s s s
VDSS 100 V
RDS(on) < 0.030 Ω
ID 35 A
TYPICAL RDS(on) = 0.025Ω IMPROVED DIE-TO-FOOTPRINT RATIO VERY LOW PROFILE PACKAGE
DESCRIPTION This Power MOSFET is the second generation of STMicroelectronics unique “STripFET™” technology. The resulting
transistor shows extremely low onresistance and minimal gate charge. The new PowerFLAT™ package allows a significant reduction in board space without compromising performance.
PowerFLAT™(6x5) (Chip Scale Package)
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS s HIGH EFFICIENCY ISOLATED DC/DC CONVETERS
ABSOLUTE MAXIMUM RATINGS
Symbol VDS VDGR VGS ID IDM (q) PTOT EAS (1) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuos) at TC = 25°C Drain Current (continuos) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature Value 100 100 ± 20 35 22 140 80 0.64 135 –65 to 150 –55 to 150 Unit V V V A A A W W/°C mJ °C °C
(q) Pulse width limited by safe operating area
(1) Starting Tj = 25°C, ID = 35A, VDD = 50V
August 2001
1/6
STL35NF10
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THERMAL DATA
Rthj-case Rthj-amb Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max 1.56 50 °C/W °C/W
ELECTRICAL CHARACTERISTICS (TCASE = 2...