MTB12P04J3

CYStech Electronics Corp. P-Channel Logic Level Enhancement Mode Power MOSFET www.DataSheet4U.com Spec. No. : C734J3 Issued Date : 2009.07.09 Revised Date : Page No. : 1/7 MTB12P04J3 Features Low Gate Charge Simple Drive Requirement Pb-free lead plating & Halogen-free package BVDSS ID RDSON(MAX) -40V -25A 12.6mΩ Equivalent Circuit MTB12P04J3 Outline TO-252 G：Gate D：Drain S：Source G D S Absolute Maximum Ratings (TC=25°C, unless otherwise noted) Parameter Symbol Limits Unit Drain-Source Voltage Gate-Source Voltage Continuous Drain Current @ TC=25°C Continuous Drain Current @ TC=100°C Pulsed Drain Current *1 Avalanche Current Avalanche Energy @ L=0.1mH, ID=-25A, RG=25Ω Repetitive Avalanche Energy @ L=0.05mH *2 Total Power Dissipation @TC=25℃ Total Power Dissipation @TC=100℃ Operating Junction and Storage Temperature Range Note : *1. Pulse width limited by maximum junction temperature *2. Duty cycle ≤ 1% MTB12P04J3 VDS VGS ID ID IDM IAS EAS EAR Pd Tj, Tstg -40 ±20 -25 -18 -100 -25 31.25 15 50 17 -55~+175 V A mJ W °C CYStek Product Specification CYStech Electronics Corp. Thermal Data Parameter Thermal Resistance, Junction-to-case, max Thermal Resistance, Junction-to-ambient, max Symbol Rth,j-c Rth,j-a www.DataSheet4U.com Spec. No. : C734J3 Issued Date : 2009.07.09 Revised Date : Page No. : 2/7 Value 2.5 75 Unit °C/W °C/W Characteristics (Tc=25°C, unless otherwise specified) Symbol Static BVDSS VGS(th) IGSS IDSS ID(ON) RDS(ON) *1 *1 Min. -40 -1.0 -25 - ...