18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM
CY7C1371D CY7C1373D
18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM with NoBL™ Architecture
18-Mbit (512 K × 36/1 M × 1...
Description
CY7C1371D CY7C1373D
18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM with NoBL™ Architecture
18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture
Features
■ No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles
■ Supports up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock
■ Pin-compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need
to use OE ■ Registered inputs for flow through operation ■ Byte write capability ■ 3.3 V/2.5 V I/O power supply (VDDQ) ■ Fast clock-to-output times
❐ 6.5 ns (for 133-MHz device) ■ Clock enable (CEN) pin to enable clock and suspend operation ■ Synchronous self-timed writes ■ Asynchronous output enable ■ Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free
and non Pb-free 119-ball BGA, and 165-ball FBGA packages ■ Three chip enables for simple depth expansion ■ Automatic power-down feature available using ZZ mode or CE
deselect ■ IEEE 1149.1 JTAG-compatible boundary scan ■ Burst capability – linear or interleaved burst order ■ Low standby power
Functional Description
The CY7C1371D/CY7C1373D is a 3.3 V, 512 K × 36/1 M × 18 synchronous flow through burst SRAM designed specifically to support unlimited true back-to-back read/write operations with no wait state insertion. The CY7C1371D/CY7C1373D is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read/wri...
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