DatasheetsPDF.com

CY7C1463AV25 Dataheets PDF



Part Number CY7C1463AV25
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description Flow-Through SRAM
Datasheet CY7C1463AV25 DatasheetCY7C1463AV25 Datasheet (PDF)

CY7C1461AV25 CY7C1463AV25 www.DataSheet4U.com CY7C1465AV25 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM with NoBL™ Architecture Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin-compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs .

  CY7C1463AV25   CY7C1463AV25



Document
CY7C1461AV25 CY7C1463AV25 www.DataSheet4U.com CY7C1465AV25 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM with NoBL™ Architecture Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin-compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 2.5V/1.8V I/O power supply • Fast clock-to-output times — 6.5 ns (for 133-MHz device) • Clock Enable (CEN) pin to enable clock and suspend operation • Synchronous self-timed writes • Asynchronous Output Enable • CY7C1461AV25, CY7C1463AV25 available in JEDEC-standard lead-free 100-pin TQFP package, lead-free and non-lead-free 165-ball FBGA package. CY7C1465AV25 available in lead-free and non-lead-free 209-ball FBGA package. • Three chip enables for simple depth expansion • Automatic Power-down feature available using ZZ mode or CE deselect • IEEE 1149.1 JTAG-Compatible Boundary Scan • Burst Capability—linear or interleaved burst order • Low standby power Functional Description[1] The CY7C1461AV25/CY7C1463AV25/CY7C1465AV25 are 2.5V, 1M × 36/2M × 18/512K × 72 Synchronous Flow-through Burst SRAMs designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1461AV25/CY7C1463AV25/ CY7C1465AV25 is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device). Write operations are controlled by the two or four Byte Write Select (BWX) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. Selection Guide 133 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 6.5 270 120 100 MHz 8.5 250 120 Unit ns mA mA Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05355 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 22, 2006 CY7C1461AV25 CY7C1463AV25 CY7C1465AV25 www.DataSheet4U.com Logic Block Diagram – CY7C1461AV25 (1M × 36) A0, A1, A MODE CLK CEN C CE ADV/LD C WRITE ADDRESS REGISTER ADDRESS REGISTER A1 D1 A0 D0 Q1 A1' A0' Q0 BURST LOGIC ADV/LD BWA BWB BWC BWD WE WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S D A T A S T E E R I N G O U T P U T B U F F E R S E DQs DQPA DQPB DQPC DQPD OE CE1 CE2 CE3 ZZ 1 INPUT E REGISTER READ LOGIC SLEEP CONTROL Logic Block Diagram – CY7C1463AV25 (2M × 18) ADDRESS REGISTER CE A0, A1, A MODE CLK CEN C A1 D1 A0 D0 ADV/LD C WRITE ADDRESS REGISTER BURST LOGIC Q1 A1' A0' Q0 ADV/LD BWA BWB WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S D A T A S T E E R I N G O U T P U T B U F F E R S E DQs DQPA DQPB WE OE CE1 CE2 CE3 ZZ INPUT E REGISTER READ LOGIC SLEEP CONTROL Document #: 38-05355 Rev. *E Page 2 of 29 CY7C1461AV25 CY7C1463AV25 CY7C1465AV25 www.DataSheet4U.com 2 Logic Block Diagram – CY7C1465AV25 (512K × 72) ADDRESS REGISTER 0 A0, A1, A MODE CLK CEN A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 ADV/LD BWa BWb BWc BWd BWe BWf BWg BWh WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S O U T P U T R E G I S T E R S D A T A S T E E R I N G O U T P U T B U F F E R S E E DQs DQPa DQPb DQPc DQPd DQPe DQPf DQPg DQPh WE INPUT REGISTER 1 E INPUT REGISTER 0 E OE CE1 CE2 CE3 ZZ READ LOGIC Sleep Control Document #: 38-05355 Rev. *E Page 3 of 29 CY7C1461AV25 CY7C1463AV25 CY7C1465AV25 www.DataSheet4U.com Pin Configurations 100-pin TQFP Pinout BWD BWC BWB BWA CE1 CE2 CE3 VDD VSS CEN CLK WE OE ADV/LD A 82 A 100 A 99 A 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 A BYTE C BYTE D DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ D.


CY7C1461AV25 CY7C1463AV25 CY7C1465AV25


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)