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CY7C1461AV33 www.DataSheet4U.com CY7C1463AV33, CY7C1465AV33
36 Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL™ Architecture
Features
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Functional Description
The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33[1] are 3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-Through Burst SRAMs designed specifically to support unlimited true back-to-back read and write operations without the insertion of wait states. The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is equipped with the advanced NoBL logic required to enable consecutive read and write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133 MHz device). Write operations are controlled by the two or four Byte Write Select (BWX) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.
No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles Supports up to 133 MHz bus operations with zero wait states ❐ Data is transferred on every clock Pin compatible and functionally equivalent to ZBT™ devices Internally self timed output buffer control to eliminate the need to use OE Registered inputs for flow through operation Byte write capability 3.3V and 2.5V IO power supply Fast clock-to-output times ❐ 6.5 ns (for 133 MHz device) Clock Enable (CEN) pin to enable clock and suspend operation Synchronous self timed writes Asynchronous Output Enable CY7C1461AV33, CY7C1463AV33 available in JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and non Pb-free 165-Ball FBGA package. CY7C1465AV33 available in Pb-free and non-Pb-free 209-Ball FBGA package Three chip enables for simple depth expansion Automatic power down feature available using ZZ mode or CE deselect IEEE 1149.1 JTAG-compatible boundary scan Burst capability — linear or interleaved burst order Low standby power
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Selection Guide
133 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 6.5 310 120 100 MHz 8.5 290 120 Unit ns mA mA
Note 1. For best practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05356 Rev. *G
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198 Champion Court
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San Jose, CA 95134-1709
• 408-943-2600 Revised May 05, 2008
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Logic Block Diagram – CY7C1461AV33 (1M x 36)
A0, A1, A MODE CLK CEN C CE ADV/LD C WRITE ADDRESS REGISTER ADDRESS REGISTER A1 D1 A0 D0 Q1 A1' A0' Q0
BURST LOGIC
ADV/LD BW A BW B BW C BW D WE WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY
S E N S E A M P S
D A T A S T E E R I N G
O U T P U T B U F F E R S E
DQs DQP A DQP B DQP C DQP D
OE CE1 CE2 CE3 ZZ
INPUT REGISTER READ LOGIC
E
SLEEP CONTROL
Logic Block Diagram – CY7C1463AV33 (2M x 18)
A0, A1, A MODE CLK CEN C CE ADV/LD C WRITE ADDRESS REGISTER ADDRESS REGISTER A1 D1 A0 D0 Q1 A1' A0' Q0
BURST LOGIC
ADV/LD BW A BW B WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY
S E N S E A M P S
D A T A S T E E R I N G
O U T P U T B U F F E R S E
DQs DQP A DQP B
WE
OE CE1 CE2 CE3 ZZ
INPUT REGISTER READ LOGIC
E
SLEEP CONTROL
Document #: 38-05356 Rev. *G
Page 2 of 32
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Logic Block Diagram – CY7C1465AV33 (512K x 72)
ADDRESS REGISTER CE
A0, A1, A MODE CLK CEN C
A1 D1 A0 D0 ADV/LD C WRITE ADDRESS REGISTER
BURST LOGIC
Q1 A1' A0' Q0
ADV/LD BW a BW b BW c BW d BW e BW f BW g BW h WE
WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC
WRITE DRIVERS
MEMORY ARRAY
S E N S E A M P S
D A T A S T E E R I N G
O U T P U T B U F F E R S E
DQs DQP a DQP b DQP c DQP d DQP e DQP f DQP g DQP h
OE CE1 CE2 CE3 ZZ
INPUT REGISTER READ LOGIC
E
SLEEP CONTROL
Document #: 38-05356 Rev. *G
Page 3 of 32
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Pin Configurations
100-Pin TQFP Pinout
ADV/LD
BWD
BWC
BWB
BWA
CE1
CE2
CE3
VDD
VSS
CEN
CLK
WE
OE
A 82
A
100
A
99
A
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
A
BYTE C
BYTE D
DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD
1 2 3 4 5 6 7 .