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H5TQ4G83AMR-xxC Dataheets PDF



Part Number H5TQ4G83AMR-xxC
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 4Gb DDR3 SDRAM
Datasheet H5TQ4G83AMR-xxC DatasheetH5TQ4G83AMR-xxC Datasheet (PDF)

4Gb DDR3 SDRAM www.DataSheet4U.com 4Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TQ4G43AMR-xxC H5TQ4G83AMR-xxC * Hynix Semiconductor reserves the right to change products or specifications without notice. Rev. 1.0 / Dec. 2009 1 www.DataSheet4U.com Revision History Revision No. 0.1 0.2 1.0 History Initial Release Updated IDD Specification JEDEC Update Draft Date Feb. 2009 Apr. 2009 Dec. 2009 Remark Rev. 1.0 / Dec. 2009 2 www.DataSheet4U.com Description The H5TQ4G43AMR-xxC, H5.

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4Gb DDR3 SDRAM www.DataSheet4U.com 4Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TQ4G43AMR-xxC H5TQ4G83AMR-xxC * Hynix Semiconductor reserves the right to change products or specifications without notice. Rev. 1.0 / Dec. 2009 1 www.DataSheet4U.com Revision History Revision No. 0.1 0.2 1.0 History Initial Release Updated IDD Specification JEDEC Update Draft Date Feb. 2009 Apr. 2009 Dec. 2009 Remark Rev. 1.0 / Dec. 2009 2 www.DataSheet4U.com Description The H5TQ4G43AMR-xxC, H5TQ4G83AMR-xxC are a 4,294,967,29-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. Hynix 4Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Device Features and Ordering Information FEATURES • VDD=VDDQ=1.5V +/- 0.075V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 6, 7, 8, 9, 10 and (11) supported • Programmable additive latency 0, CL-1, and CL-2 supported • Programmable CAS Write latency (CWL) = 5, 6, 7, 8 • Programmable burst length 4/8 with both nibble sequential and interleave mode • BL switch on the fly • 8banks • Average Refresh Cycle (Tcase of 0 oC~ 95 oC) - 7.8 µs at 0oC ~ 85 oC - 3.9 µs at 85oC ~ 95 oC • Auto Self Refresh supported • JEDEC standard 82ball FBGA(x4/x8) • Driver strength selected by EMRS • Dynamic On Die Termination supported • Asynchronous RESET pin supported • ZQ calibration supported • TDQS (Termination Data Strobe) supported (x8 only) • Write Levelization supported • 8 bit pre-fetch * This product in compliance with the RoHS directive. Rev. 1.0 / Dec. 2009 3 www.DataSheet4U.com ORDERING INFORMATION Part No. H5TQ4G43AMR-*xxC H5TQ4G83AMR-*xxC Configuration 1G x 4 512M x 8 Package 82ball FBGA OPERATING FREQUENCY Speed Grade (Marking) -G7 -H9 Frequency [MHz] CL5 CL6 O O CL7 O O CL8 O O O O CL9 CL10 CL11 Remark (CL-tRCD-tRP) DDR3-1066 7-7-7 DDR3-1333 9-9-9 * xx means Speed Bin Grade Rev. 1.0 / Dec. 2009 4 www.DataSheet4U.com Package Ballout/Mechanical Dimension x4 Package Ball out (Top view): 82ball FBGA Package 1 A B C D E F G H J K L M N NC 1 NC 2 VSS VSS VDDQ VSSQ VREFDQ ODT1 ODT0 CS1 VSS VDD VSS VDD VSS 2 3 VDD VSSQ DQ2 NF VDDQ VSS VDD CS0 BA0 A3 A5 A7 RESET 3 4 NC DQ0 DQS DQS NF RAS CAS WE BA2 A0 A2 A9 A13 4 5 6 7 5 6 7 8 NF DM DQ1 VDD NF CK CK A10/AP NC A12/BC A1 A11 A14 8 9 VSS VSSQ DQ3 VSS NF VSS VDD ZQ0 VREFCA BA1 A4 A6 A8 9 10 VDD VDDQ VSSQ VSSQ VDDQ CKE1 CKE0 ZQ1 VSS VDD VSS VDD VSS 10 NC 11 11 NC A B C D E F G H J K L M N Note: NF (No Function) - This is applied to balls only used in x4 configuration. 1 2 3 4 A B C D E F G H J K L M N 8 9 10 11 (Top View: See the balls through the Package) Populated ball Ball not populated Rev. 1.0 / Dec. 2009 5 www.DataSheet4U.com x8 Package Ball out (Top view): 82ball FBGA Package 1 A B C D E F G H J K L M N NC 1 NC 2 VSS VSS VDDQ VSSQ VREFDQ ODT1 ODT0 CS1 VSS VDD VSS VDD VSS 2 3 VDD VSSQ DQ2 DQ6 VDDQ VSS VDD CS0 BA0 A3 A5 A7 RESET 3 4 NC DQ0 DQS DQS DQ4 RAS CAS WE BA2 A0 A2 A9 A13 4 5 6 7 5 6 7 8 NF/TDQS DM/TDQS DQ1 VDD DQ7 CK CK A10/AP NC A12/BC A1 A11 A14 8 9 VSS VSSQ DQ3 VSS DQ5 VSS VDD ZQ0 VREFCA BA1 A4 A6 A8 9 10 VDD VDDQ VSSQ VSSQ VDDQ CKE1 CKE0 ZQ1 VSS VDD VSS VDD VSS 10 NC 11 11 NC A B C D E F G H J K L M N 1 2 3 4 A B C D E F G H J K L M N 8 9 10 11 (Top View: See the balls through the Package) Populated ball Ball not populated Rev. 1.0 / Dec. 2009 6 www.DataSheet4U.com Pin Functional Description Symbol CK, CK Type Input Function Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable during the power on and initialization sequence, they must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE, are disabled during powerdown. Input buffers, excluding CKE, are .


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