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HMT164S6AFR6C Dataheets PDF



Part Number HMT164S6AFR6C
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 204pin DDR3 SDRAM SODIMMs
Datasheet HMT164S6AFR6C DatasheetHMT164S6AFR6C Datasheet (PDF)

www.DataSheet4U.com 204pin DDR3 SDRAM SODIMMs DDR3 SDRAM Unbuffered SODIMMs Based on 1Gb A version HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C ** Contents are subject to change without prior notice. Rev. 0.2 / Dec. 2008 1 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C www.DataSheet4U.com Revision History Revision No. 0.01 0.02 0.03 0.1 0.2 History Initial draft Added IDD, corrected typos Halogen-free added Initial Specification Release Added outline: DIMMs with thermal sensor..

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www.DataSheet4U.com 204pin DDR3 SDRAM SODIMMs DDR3 SDRAM Unbuffered SODIMMs Based on 1Gb A version HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C ** Contents are subject to change without prior notice. Rev. 0.2 / Dec. 2008 1 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C www.DataSheet4U.com Revision History Revision No. 0.01 0.02 0.03 0.1 0.2 History Initial draft Added IDD, corrected typos Halogen-free added Initial Specification Release Added outline: DIMMs with thermal sensor. Corrected typo on package ball feature. Draft Date Sep. 2007 Mar. 2008 May. 2008 May 2008 Dec. 2008 Remark preliminary preliminary preliminary Rev. 0.2 / Dec. 2008 2 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C www.DataSheet4U.com Table of Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.2 Speed Grade & Key Parameters 1.3 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1 512MB, 64Mx64 Module(1Rank of x16) 3.2 1GB, 128Mx64 Module(2Rank of x16) 3.3 2GB, 256Mx64 Module(2Rank of x8) 4. Absolute Maximum Ratings 4.1 Absolute Maximum DC Ratings 4.2 Operating Temperature Range 5. AC & DC Operating Conditions 5.1 Recommended DC Operating Conditions 5.2 DC & AC Logic Input Levels 5.2.1 For Single-ended Signals 5.2.2 For Differential Signals 5.2.3 Differential Input Cross Point 5.3 Slew Rate Definition 5.3.1 For Ended Input Signals 5.3.2 For Differential Input Signals 5.4 DC & AC Output Buffer Levels 5.4.1 Single Ended DC & AC Output Levels 5.4.2 Differential DC & AC Output Levels 5.4.3 Single Ended Output Slew Rate 5.4.4 Differential Ended Output Slew Rate 5.5 Overshoot/Undershoot Specification 5.5.1 Address and Control Overshoot and Undershoot Specifications 5.5.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications 5.6 Input/Output Capacitance & AC Parametrics 5.7 IDD Specifications & Measurement Conditions 6. Electrical Characteristics and AC Timing 6.1 Refresh Parameters by Device Density 6.2 DDR3 Standard speed bins and AC para 7. DIMM Outline Diagram 7.1 512MB, 64Mx64 Module(1Rank of x16) 7.2 1GB, 128Mx64 Module(2Rank of x16) 7.3 2GB, 256Mx64 Module(2Rank of x8) Rev. 0.2 / Dec. 2008 3 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C www.DataSheet4U.com 1. Description This Hynix unbuffered Small Outline Dual In-Line Memory Module (SODIMM) series consists of 1Gb A version. DDR3 SDRAMs in Fine Ball Grid Array (FBGA) packages on a 204 pin glass-epoxy substrate. This DDR3 Unbuffered SODIMM series based on 1Gb A version provide a high performance 8 byte interface in 67.60mm width form factor of industry standard. It is suitable for easy interchange and addition. 1.1 Device Features & Ordering Information 1.1.1 Features • VDD=VDDQ=1.5V • VDDSPD=3.0V to 3.6V • Fully differential clock inputs (CK, /CK) operation • Differential Data Strobe (DQS, /DQS) • On chip DLL align DQ, DQS and /DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11) supported • Programmable additive latency 0, CL-1 and CL-2 supported • Programmable CAS Write latency (CWL) = 5, 6, 7, 8 • Programmable burst length 4/8 with both nibble sequential and interleave mode • BL switch on the fly • 8 banks • 8K refresh cycles /64ms • DDR3 SDRAM Package: JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16) • Driver strength selected by EMRS • Dynamic On Die Termination supported • Asynchronous RESET pin supported • ZQ calibration supported • TDQS (Termination Data Strobe) supported (x8 only) • Write Levelization supported • Auto Self Refresh supported • 8 bit pre-fetch Rev. 0.2 / Dec. 2008 4 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C www.DataSheet4U.com 1.1.2 Ordering Information # of DRAMs 4 4 8 8 16 16 # of ranks 1 1 2 2 2 2 Part Name HMT164S6AFP6C-S6/S5/G8/G7/H9/H8 HMT164S6AFR6C-S6/S5/G8/G7/H9/H8 HMT112S6AFP6C-S6/S5/G8/G7/H9/H8 HMT112S6AFR6C-S6/S5/G8/G7/H9/H8 HMT125S6AFP8C-S6/S5/G8/G7/H9/H8 HMT125S6AFR8C-S6/S5/G8/G7/H9/H8 Density 512MB 512MB 1GB 1GB 2GB 2GB Organization 64Mx64 64Mx64 128Mx64 128Mx64 256Mx64 256Mx64 Materials Lead free Halogen free Lead free Halogen free Lead free Halogen free Two types, with integrated thermal sensor and with no thermal sensor, exist in each configuration. Rev. 0.2 / Dec. 2008 5 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C w w w . D a t a S 1.2 Speed Grade & Key Parameters MT/S Grade tCK (min) CAS Latency tRCD (min) tRP (min) tRAS (min) tRC (min) CL-tRCD-tRP 6 15 15 37.5 52.5 6-6-6 DDR3-800 -S6 2.5 5 12.5 12.5 37.5 50 5-5-5 8 15 15 37.5 52.5 8-8-8 -S5 DDR3-1066 -G8 1.875 7 13.125 13.125 37.5 50.625 7-7-7 9 13.5 13.5 36 49.5 9-9-9 -G7 DDR3-1333 Unit -H9 1.5 8 12 12 36 48 8-8-8 -H8 n.


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