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240pin DDR3 SDRAM VLP Registered DIMM
DDR3 SDRAM VLP Registered DIMM Based on 1Gb A version
HMT112V7AFP8C HMT125V7AFP8C HMT125V7AFP4C HMT351V7AMP4C
** Contents may be changed at any time without any notice.
Rev. 0.2 / December 2008
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Revision History
Revision No. 0.1 0.2 History Initial Release Added IDD, corrected typos Draft Date 2008-8 2008-12 Remark
Rev. 0.2 / December 2008
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Table of Contents
1. Description 1.1 Device Features and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.2 Speed Grade & Key Parameters 1.3 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1 1GB, 128Mx72 Module(1Rank 3.2 2GB, 256Mx72 Module(2Rank 3.3 2GB, 256Mx72 Module(1Rank 3.4 4GB, 512Mx72 Module(2Rank of of of of x8) x8) x4) x4)
4. Input/Output Capacitance & AC Parametrics 5. IDD Specifications 6. DIMM Outline Diagram 6.1 1GB, 128Mx72 Module(1Rank 6.2 2GB, 256Mx72 Module(2Rank 6.3 2GB, 256Mx72 Module(1Rank 6.4 4GB, 512Mx72 Module(2Rank of of of of x8) x8) x4) x4)
Rev. 0.2 / December 2008
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1. Description
This Hynix DDR3 VLP (Very Low Profile) registered Dual In-Line Memory Module (DIMM) series consists of 1Gb A generation. These are intended for use as main memory in server and workstation systems, providing a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition.
1.1 Device Features & Ordering Information
1.1.1 Features
• VDD=VDDQ=1.5V • VDDSPD=3.3V to 3.6V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and /DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11) supported • Programmable additive latency 0, CL-1, and CL-2 sup ported • Programmable CAS Write latency (CWL) = 5, 6, 7, 8 • Programmable burst length 4/8 with both nibble sequential and interleave mode • BL switch on the fly • 8banks • 8K refresh cycles /64ms • DDR3 SDRAM Package: JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16) with support balls • Driver strength selected by EMRS • Dynamic On Die Termination supported • Asynchronous RESET pin supported • ZQ calibration supported • TDQS (Termination Data Strobe) supported (x8 only) • Write Levelization supported • Auto Self Refresh supported • 8 bit pre-fetch • Heat Spreader installed for 4GB • SPD with Integrated TS of Class B
1.1.2 Ordering Information
# of DRAMs 9 18 18 36 # of ranks 1 2 1 2
Part Name HMT112V7AFP8C-G7/H9 HMT125V7AFP8C-G7/H9 HMT125V7AFP4C-G7/H9 HMT351V7AMP4C-G7/H9
Density 1GB 2GB 2GB 4GB
Organization 128Mx72 256Mx72 256Mx72 512Mx72
Materials Lead free Lead free Lead free Lead free
FDHS X X X O
*Please Contact local sales administrator for more details of part number
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1.2 Speed Grade & Key Parameters
MT/S Grade tCK (min) CAS Latency tRCD (min) tRP (min) tRAS (min) tRC (min) CL-tRCD-tRP DDR3-1066 -G7 1.875 7 13.125 13.125 37.5 50.625 7-7-7 DDR3-1333 Unit -H9 1.5 9 13.5 13.5 36 49.5 9-9-9 ns tCK ns ns ns ns tCK
1.3 Address Table
1GB(1Rx8) Organization Refresh Method Row Address Column Address Bank Address Page Size # of Rank # of Device 128M x 72 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 1 9 2GB(2Rx8) 256M x 72 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 2 18 2GB(1Rx4) 256M x 72 8K/64ms A0-A13 A0-A9,A11 BA0-BA2 1KB 1 18 4GB(2Rx4) 512M x 72 8K/64ms A0-A13 A0-A9,A11 BA0-BA2 1KB 2 36
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2. Pin Architecture
2.1 Pin Definition
Pin Name A0–A9,A11 A13-A15 BA0–BA2 RAS CAS WE S0–S3 CKE0–CKE1 ODT0–ODT1 DQ0–DQ63 CB0–CB7 DQS0–DQS8 DQS0–DQS8 Description Address Inputs SDRAM Bank Addresses Row Address Strobe Column Address Strobe Write Enable Chip Selects Clock Enables On-die termination Inputs Data Input/Output Data Check Bits Input/Output Data Strobes Data Strobes, Negative Line Num -ber 14 3 1 1 1 4 2 2 64 8 9 9 9 Pin Name A10/AP A12/BC SCL SDA SA0–SA2 Par_in ERR_OUT EVENT TEST RESET VDD VSS VREFDQ VREFCA VTT 9 1 1 VDDSPD CK1 CK1 Description Address Input/Autoprecharge Address Input/Autoprecharge Serial Presence Detect (SPD) Clock Input SPD Data Input/Output SPD Address Inputs Parity Bit For The Address and Control Bus Parity Error Found on the Address and Control Bus Reserved for Optional Hardware temperature Sensing Memory Bus Test Tool (Not Connected and Not Usable on DIMMs) Register and SDRAM control pin Power Supply Ground Reference Voltage for DQ Reference Voltage for CA Termination Voltage SPD Power Clock Input, positive line Clock Input, negative line Num -ber 1 1 1 1 3 1 1 1 1 1 22 59 1 1 4 1 1 1
Data Masks DM0–DM8 DQS9-DQ.