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HYMD132G725EL4-H Dataheets PDF



Part Number HYMD132G725EL4-H
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description Registered DDR SDRAM DIMM
Datasheet HYMD132G725EL4-H DatasheetHYMD132G725EL4-H Datasheet (PDF)

www.DataSheet4U.com 32Mx72 bits Registered DDR SDRAM DIMM HYMD132G725E(L)4-M/K/H/L DESCRIPTION Preliminary Hynix HYMD132G725E(L)4-M/K/H/L series is registered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 32Mx72 high-speed memory arrays. Hynix HYMD132G725E(L)4-M/ K/H/L series consists of eighteen 32Mx4 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD132G725E(L)4-M/K/H/L series provide a high performance 8.

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www.DataSheet4U.com 32Mx72 bits Registered DDR SDRAM DIMM HYMD132G725E(L)4-M/K/H/L DESCRIPTION Preliminary Hynix HYMD132G725E(L)4-M/K/H/L series is registered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 32Mx72 high-speed memory arrays. Hynix HYMD132G725E(L)4-M/ K/H/L series consists of eighteen 32Mx4 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD132G725E(L)4-M/K/H/L series provide a high performance 8-byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition. Hynix HYMD132G725E(L)4-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system. Hynix HYMD132G725E(L)4-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer. FEATURES • • • • • • • 256MB (32M x 72) Registered DDR DIMM based on 32Mx4 DDR SDRAM JEDEC Standard 184-pin dual in-line memory module (DIMM) Error Check Correction (ECC) Capability Registered inputs with one-clock delay Phase-lock loop (PLL) clock driver to reduce loading 2.5V +/- 0.2V VDD and VDDQ Power supply All inputs and outputs are compatible with SSTL_2 interface • • • • • • • Fully differential clock operations (CK & /CK) with 100MHz/125MHz/133MHz Programmable CAS Latency 2 / 2.5 supported Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode tRAS Lock-out function supported Internal four bank operations with single pulsed RAS Auto refresh and self refresh supported 4096 refresh cycles / 64ms ORDERING INFORMATION Part No. HYMD132G725E(L)4-M HYMD132G725E(L)4-K HYMD132G725E(L)4-H HYMD132G725E(L)4-L VDD=2.5V VDDQ=2.5V Power Supply Clock Frequency 133MHz (*DDR266:2-2-2) 133MHz (*DDR266A) 133MHz (*DDR266B) 125MHz (*DDR200) Interface Form Factor SSTL_2 184pin Registered DIMM 5.25 x 1.7 x 0.15 inch * JEDEC Defined Specifications compliant This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 / Sep. 2003 1 HYMD132G725E(L)4-M/K/H/L PIN DESCRIPTION Pin CK0, /CK0 CS0 CKE0 /RAS, /CAS, /WE A0 ~ A11 BA0, BA1 DQ0~DQ63 CB0~CB7 DQS0~DQS17 DM0~8 VDD /RESET Pin Description Differential Clock Inputs Chip Select Input Clock Enable Input Commend Sets Inputs Address Bank Address Data Inputs/Outputs Data Strobe Inputs/Outputs Data Strobe Inputs/Outputs Data-In Mask Power Supply Reset Enable Pin VDDQ VSS VREF VDDSPD SA0~SA2 SCL SDA WP VDDID DU NC FETEN Pin Description DQs Power Supply Ground Reference Power Supply Power Supply for SPD E2PROM Address Inputs E2PROM Clock E2PROM Data I/O Write Protect Flag VDD Identification Flag Do not Use No Connection FET Enable www.DataSheet4U.com PIN ASSIGNMENT Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Name VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC /RESET VSS DQ8 DQ9 DQS1 VDDQ DU DU VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 53 54 55 56 57 58 59 60 61 Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Key DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 Name A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 Vss A1 CB0 CB1 VDD DQS8 A0 CB2 VSS CB3 BA1 Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Name VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 VSS DU DU VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS WP SDA SCL Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Name VSS DQ4 DQ5 VDDQ DQS9 DQ6 DQ7 VSS NC NC A13* VDDQ DQ12 DQ13 DQS10 VDD DQ14 DQ15 CKE1* VDDQ BA2* DQ20 A12* VSS DQ21 A11 DQS11 VDD DQ22 A8 DQ23 145 146 147 148 149 150 151 152 153 Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 key VSS DQ36 DQ37 VDD DQS13 DQ38 DQ39 VSS DQ44 Name VSS A6 DQ28 DQ29 VDDQ DQS12 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 /CK0 VSS DQS17 A10 CB6 VDDQ CB7 Pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184.


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