Document
128Mx64 bits Unbuffered DDR SO-DIMM HYMD512M646A(L)FS8-D43/D4
Document Title 128Mx64 bits Unbuffered DDR SO-DIMM Revision History
No. 0.1 0.2 Initial Draft 1) Reflected a “notational” change in module thickness on page 14 - Not Real ! 2) Corrected some typos History Draft Date Dec. 2003 Apr. 2004 Remark
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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / Apr. 2004 1
128Mx64 bits Unbuffered DDR SO-DIMM HYMD512M646A(L)FS8-D43/D4
DESCRIPTION
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Hynix HYMD512M646A(L)FS8-D43/D4 series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline Dual In-Line Memory Modules (SO-DIMMs) which are organized as 128Mx64 high-speed memory arrays. Hynix HYMD512M646A(L)FS8-D43/D4 series consists of eight 128Mx8 DDR MCP SDRAM in FBGA packages on a 200pin glass-epoxy substrate. Hynix HYMD512M646A(L)FS8-D43/D4 series provide a high performance 8-byte interface in 67.60mmX 31.75mm form factor of industry standard. It is suitable for easy interchange and addition. Hynix HYMD512M646A(L)FS8-D43/D4 series is designed for high speed of up to 200MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system. Hynix HYMD512M646A(L)FS8-D43/D4 series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
• • • • • • 1GB (128M x 64) Unbuffered DDR SO-DIMM based on 128Mx8 DDR MCP SDRAM 200-pin small outline dual in-line memory module (SO-DIMM) 2.6V +/- 0.1V VDD and VDDQ Power supply All inputs and outputs are compatible with SSTL_2 interface Fully differential clock operations (CK & /CK) with 200MHz All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock Data(DQ), Data strobes and Write masks latched on both rising and falling edges of the clock • • • • • • • • Data inputs on DQS centers when write (centered DQ) Data strobes synchronized with output data for read and input data for write Programmable CAS Latency 3 supported Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode tRAS Lock-out function supported Internal four bank operations with single pulsed RAS Auto refresh and self refresh supported 8192 refresh cycles / 64ms
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ORDERING INFORMATION
Part No.
HYMD512M646A(L)FS8-D43 HYMD512M646A(L)FS8-D4
Power Supply
VDD=2.6V VDDQ=2.6V
Clock Frequency
200MHz (DDR400 3-3-3) 200MHz (DDR400 3-4-4)
Interface
SSTL_2
Form Factor
200pin Unbuffered SO-DIMM 67.6mm x 31.75mm x 1mm
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / Apr. 2004 2
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HYMD512M646A(L)FS8-D43/D4
PIN DESCRIPTION
Pin CK0, /CK0, CK1, /CK1 CS0, CS1 CKE0, CKE1 /RAS, /CAS, /WE A0 ~ A12 BA0, BA1 DQ0~DQ63 DQS0~DQS7 DM0~DM7 VDD Pin Description Differential Clock Inputs Chip Select Input Clock Enable Input Commend Sets Inputs Address Bank Address Data Inputs/Outputs Data Strobe Inputs/Outputs Data-in Mask Power Supply Pin VDDQ VSS VREF VDDSPD SA0~SA2 SCL SDA VDDID DU NC Pin Description DQs Power Supply Ground Reference Power Supply Power Supply for SPD E2PROM Address Inputs E2PROM Clock E2PROM Data I/O VDD Identification Flag Do not Use No Connection
PIN ASSIGNMENT
Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Name VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 /CK0 VSS DQ16 DQ17 VDD DQS2 DQ18 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Name VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS DQ20 DQ21 VDD DM2 DQ22 Pin 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 Name VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD NC NC VSS NC NC VDD NC DU VSS NC NC VDD CKE1 NC A12 Pin 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 Name VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD NC NC VSS NC NC VDD NC DU VSS VSS VDD VDD CKE0 DU .