2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
IDT5T905 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
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2.5V SINGL...
Description
IDT5T905 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
www.DataSheet4U.com
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFERâ„¢
FEATURES:
IDT5T905
DESCRIPTION:
Guaranteed Low Skew < 25ps (max) Very low duty cycle distortion High speed propagation delay < 2.5ns. (max) Up to 250MHz operation Very low CMOS power levels 1.5V VDDQ for HSTL interface Hot insertable and over-voltage tolerant inputs 3-level inputs for selectable interface Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input interface Selectable differential or single-ended inputs and five singleended outputs 2.5V VDD Available in TSSOP package
The IDT5T905 2.5V single data rate (SDR) clock buffer is a user-selectable single-ended or differential input to five single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fanout from a single or differential input to five single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. The IDT5T905 can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. Multiple power and grounds reduce noise.
Clock and signal distribution
APPLICATIONS:
FUNCTIONAL BLOCK DIAGRAM
TxS GL G
OUTPUT CONTROL
Q1
RxS A ...
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