IDT5T9310

IDT5T9310 2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II INDUSTRIAL TEMPERATURE RANGE www.DataSheet4U.com 2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER™ II FEATURES: IDT5T9310 DESCRIPTION: Guaranteed Low Skew < 25ps (max) Very low duty cycle distortion < 125ps (max) High speed propagation delay < 1.75ns (max) Up to 1GHz operation Selectable inputs Hot insertable and over-voltage tolerant inputs 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input interface Selectable differential inputs to ten LVDS outputs Power-down mode 2.5V VDD Available in VFQFPN package The IDT5T9310 2.5V differential clock buffer is a user-selectable differential input to ten LVDS outputs. The fanout from a differential input to ten LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The IDT5T9310 can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for an asynchronous change-over from a primary clock source to a secondary clock source. Selectable reference inputs are controlled by SEL. The IDT5T9310 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise. APPLICATIONS: Clock distribution FUNCTIONAL BLOCK...